traplog.tlg

自己实用Verilog编写的UART程序

@N: CD630 :".\gentmp0a02992":4:7:4:9|Synthesizing work.top.gen 
@N: CD630 :"syng0a02992":670:7:670:9|Synthesizing work.add.fbk 
@N: CD630 :"syng0a02992":12:7:12:21|Synthesizing work.dwact_bl_genadd.generic_adder 
@W: CD280 :"syng0a02992":492:12:492:15|Unbound component AND2 mapped to black box
@W: CD280 :"syng0a02992":500:12:500:14|Unbound component OR3 mapped to black box
@W: CD280 :"syng0a02992":508:12:508:15|Unbound component XOR2 mapped to black box
@W: CD280 :"syng0a02992":515:12:515:14|Unbound component AO1 mapped to black box
@W: CD638 :"syng0a02992":37:9:37:12|Signal zero is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_0 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_1 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_2 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_3 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_4 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_5 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_6 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_7 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_8 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_9 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_10 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_11 is undriven 
@W: CD639 :"syng0a02992":486:11:486:17|Bit <0> of signal g_array_12 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_0 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_1 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_2 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_3 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_4 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_5 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_6 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_7 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_8 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_9 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_10 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_11 is undriven 
@W: CD639 :"syng0a02992":486:20:486:28|Bit <0> of signal pog_array_12 is undriven 
@W: CD638 :"syng0a02992":487:11:487:14|Signal tmp1 is undriven 
@W: CD639 :"syng0a02992":487:17:487:27|Bit <4> of signal partial_sum is undriven 
@N: CD630 :"syng0a02992":492:12:492:15|Synthesizing work.and2.syn_black_box 
Post processing for work.and2.syn_black_box
@N: CD630 :"syng0a02992":515:12:515:14|Synthesizing work.ao1.syn_black_box 
Post processing for work.ao1.syn_black_box
@N: CD630 :"syng0a02992":508:12:508:15|Synthesizing work.xor2.syn_black_box 
Post processing for work.xor2.syn_black_box
@N: CD630 :"syng0a02992":500:12:500:14|Synthesizing work.or3.syn_black_box 
Post processing for work.or3.syn_black_box
Post processing for work.dwact_bl_genadd.generic_adder
@W: CL168 :"syng0a02992":655:19:655:19|Pruning instance level_loop.11.bit_loop.2.G1_2_4_2.P - not in use ... 
@W: CL168 :"syng0a02992":655:19:655:19|Pruning instance level_loop.1.bit_loop.3.G1_2_4_2.P - not in use ... 
@W: CL168 :"syng0a02992":655:19:655:19|Pruning instance level_loop.0.bit_loop.1.G1_2_4_2.P - not in use ... 
@W: CL168 :"syng0a02992":602:8:602:9|Pruning instance misc_loop.0.P0 - not in use ... 
Post processing for work.add.fbk
Post processing for work.top.gen