uart_test.plg

自己实用Verilog编写的UART程序

@P:  Worst Slack : -0.588
@P:  send|clkout_inferred_clock - Estimated Frequency : 734.0 MHz
@P:  send|clkout_inferred_clock - Requested Frequency : 100.0 MHz
@P:  send|clkout_inferred_clock - Estimated Period : 1.362
@P:  send|clkout_inferred_clock - Requested Period : 10.000
@P:  send|clkout_inferred_clock - Slack : 8.638
@P:  uart_test|clock - Estimated Frequency : 94.5 MHz
@P:  uart_test|clock - Requested Frequency : 100.0 MHz
@P:  uart_test|clock - Estimated Period : 10.588
@P:  uart_test|clock - Requested Period : 10.000
@P:  uart_test|clock - Slack : -0.588
@P:  Total Area : 296.0
@P:  Total Area : 114.0
@P:  Total Area : 153.0
@P:  Total Area : 296.0
@P:  CPU Time : 0h:00m:02s