uart.prj

自己实用Verilog编写的UART程序

KEY LIBERO "7.3"
KEY CAPTURE "7.3.2.2"
KEY DEFAULT_IMPORT_LOC "C:\Actelprj\Uart\hdl"
KEY DEFAULT_OPEN_LOC ""
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "ProASIC3"
KEY VendorTechnology_Die "IS4X4M1"
KEY VendorTechnology_Package "pq208"
KEY ProjectLocation "E:\所有其他\安装文件\FPGA\actel\实验例程\UART"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "uart_test"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\designer\impl1\uart_test.adb,adb"
STATE="utd"
ENDFILE
VALUE "<project>\designer\impl1\uart_test.stp,stp"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\rec.v,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\send.v,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\hdl\uart_test.v,hdl"
STATE="utd"
ENDFILE
VALUE "<project>\synthesis\uart_test.edn,syn_edn"
STATE="utd"
ENDFILE
VALUE "<project>\synthesis\uart_test_sdc.sdc,syn_sdc"
STATE="utd"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST AssociatedStimulus
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
CompilePackage=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
UpdateViewDrawIni=TRUE
NoIOMode=FALSE
GenerateHDLFromSchematic=TRUE
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
Type=Synthesis
Profile=Synplify
Tool=Synplify
Location=e:\Libero\Synplify\Synplify_862H\bin\Synplify.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Simulation
Profile=ModelSim
Tool=ModelSim
Location=e:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Stimulus
Profile=WFL
Tool=WFL
Location=e:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=false
EndProfile
Type=PhySynthesis
Profile=PALACE
Tool=PALACE
Location=palace_actel.exe
AdditionalParameter=
Batch=false
EndProfile
Type=Program
Profile=FlashPro
Tool=FlashPro
Location=e:\Libero\FlashPro\bin\FlashPro.exe
AdditionalParameter=
Batch=false
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "uart_test"
LIST Impl1
LiberoState=Post_Layout
ideSYNTHESIS(<project>\synthesis\uart_test.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\uart_test.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\uart_test.edn,syn_edn"
VALUE "<project>\synthesis\uart_test_sdc.sdc,syn_sdc"
VALUE "<project>\synthesis\uart_test.v,syn_hdl"
VALUE "<project>\phy_synthesis\uart_test_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\uart_test_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\uart_test_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\uart_test_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\uart_test_palace.v,palace_hdl"
VALUE "<project>\designer\impl1\uart_test.adb,adb"
VALUE "<project>\designer\impl1\uart_test.prb,prb"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST OODAdbs
ENDLIST
LIST UserCustomizedFileList
ENDLIST