fulladder.vhd

来自「使用Vhdl语言实现数字电路全加器功能」· VHDL 代码 · 共 46 行

library ieee;
use ieee.std_logic_1164.all;
entity fulladder is port(
a1,a2,c1:in std_logic;
c2,b: out std_logic);
end fulladder;
architecture behav of fulladder is 
begin
b<=a1 xor a2 xor c1;
c2<=(a1 and a2)or(a1 and c1)or(a2 and c1);
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity adder is port(
input1,input2: in std_logic_vector(0 to 3);
carryer: out std_logic;
output: out std_logic_vector(0 to 3));
end adder;
architecture struct of adder is
component fulladder port(
a1,a2,c1: in std_logic;
c2,b: out std_logic);
end component;
signal d0,d1,d2,d3,i0,i1,i2: std_logic;
begin
d0<='0';
u0: fulladder port map(input1(0),input2(0),d0,i0,output(0));
    d1<=i0;
u1: fulladder port map(input1(1),input2(1),d1,i1,output(1));
    d2<=i1;
u2: fulladder port map(input1(2),input2(2),d2,i2,output(2));
    d3<=i2;
u3: fulladder port map(input1(3),input2(3),d3,carryer,output(3));
end struct;