entries

基于Verilog HDL 的一个CAN总线IP核。

/README.txt/1.1/Wed May 12 15:58:42 2004//
/can_acf.v/1.10/Fri Apr  8 13:03:08 2005//
/can_bsp.v/1.53/Mon Nov 22 19:18:04 2004//
/can_btl.v/1.30/Wed Oct 27 18:51:38 2004//
/can_crc.v/1.5/Sun Feb  8 14:25:58 2004//
/can_defines.v/1.14/Wed May 12 15:58:42 2004//
/can_fifo.v/1.28/Thu Mar 10 08:25:48 2005//
/can_ibo.v/1.3/Sun Feb  8 14:31:44 2004//
/can_register.v/1.7/Sun Feb  8 14:32:32 2004//
/can_register_asyn.v/1.7/Sun Feb  8 14:33:20 2004//
/can_register_asyn_syn.v/1.7/Sun Feb  8 14:34:00 2004//
/can_register_syn.v/1.5/Sun Feb  8 14:34:40 2004//
/can_registers.v/1.36/Fri Mar 18 15:04:06 2005//
/can_top.v/1.48/Mon Oct 25 11:44:48 2004//
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