entries

基于verilog HDL的一个USB 1.1的IP 核

/README/1.1/Mon May 10 19:23:26 2004//
/test_bench_8051_top.v/1.1/Mon May 10 19:23:26 2004//
/test_bench_ocp_top.v/1.1/Mon May 10 19:23:26 2004//
/tests.v/1.3/Fri May 28 23:13:16 2004//
/tests_lib.v/1.1/Mon May 10 19:23:26 2004//
/tests_ocp.v/1.3/Fri May 28 23:13:16 2004//
/usb_defines.v/1.1/Fri May 14 16:19:44 2004//
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