uart.v

Verilog实现mini-uart

//============================================================================
//
//        Title     : UART DESIGN
//        Author    : JP LIU
//
//=============================================================================
//
//        File Name      : uart.v
//        Module Name    : uart
//
//=============================================================================
// 
// Universal Asyhnchronous Receiver Transmitter
// This is a reduced version of the UART.
// It is fully functional, synthesizable, ideal for embedded system.
// 
//=============================================================================

`include "UART_INC.h"	

module UART	
(	
  // Output Port
  UART_XMIT_DATA,
  MP_DATA_FROM_UART,
  MP_INT_B,
  UART_CLK,

  // Input Port
  SYS_RST_B,
  SYS_CLK,
  MP_CLK,
  MP_CS_B,
  MP_ADDX,
  MP_DATA_TO_UART,
  UART_REC_DATA,
  MP_RD_B,
  MP_WR_B  
);





////////////////////////////////////////////////////////////

//   INPUT AND OUTPUT DECLARATION                         //
////////////////////////////////////////////////////////////			

output	[7:0]   MP_DATA_FROM_UART;        //DATA TO MCU FROM UART
output		UART_XMIT_DATA;           //DATA TO RECEIVER FROM UART
output          MP_INT_B;                 //DATA TO MCU FROM UART

output          UART_CLK;

input		SYS_RST_B;                //SYSTEM RESET
input		SYS_CLK;                  //SYSTEM CLK
input           MP_CLK;                   //MICROPROCESSOR CLK
input           MP_CS_B;                  //MINI-UART CHIP SELECT
input	[2:0]   MP_ADDX;                  //THE REGISTERS'S ADDRESS
input	[7:0]   MP_DATA_TO_UART;          //DATA TO UART FROM MCU
input           MP_RD_B;                  //READ LOW ACTIVE 
input           MP_WR_B;                  //WRITE LOW ACTIVE
input           UART_REC_DATA;            //DATA TO UART FROM TRANSMITTER

`protect


////////////////////////////////////////////////////////////

//   WIRE AND REG DECLARATION                             //
////////////////////////////////////////////////////////////

wire	[7:0]   MP_DATA_FROM_UART;
wire		UART_XMIT_DATA;
wire            MP_INT_B;

wire		SYS_RST_B;
wire		SYS_CLK;
wire            MP_CLK;
wire            MP_CS_B;
wire	[2:0]   MP_ADDX;
wire	[7:0]   MP_DATA_TO_UART;
wire            MP_RD_B;
wire            MP_WR_B;
wire            UART_REC_DATA;

wire 		UART_CLK;
wire	[15:0]	BAUD_RATE_DIV;
wire		XMIT_START_PULSE;
wire		XMIT_DONE;
wire	[7:0]	REG_XMIT_DAT;
wire	[7:0]	REC_DATA;
wire		REC_READY;


////////////////////////////////////////////////////////////

//   COMBINATIONAL LOGIC                                  //
////////////////////////////////////////////////////////////

// Instantiate the Microprocessor Interface
MP_INT I_MP_INT_0 (
                  .START_PULSE              (XMIT_START_PULSE),
                  .REG_XMIT_DAT             (REG_XMIT_DAT),
                  .BAUD_RATE_DIV            (BAUD_RATE_DIV),
                  .MP_DATA_FROM_UART        (MP_DATA_FROM_UART),
                  .MP_INT_B                 (MP_INT_B),
                  .SYS_RST_B                (SYS_RST_B),
                  .UART_CLK                 (UART_CLK),
                  .MP_CLK                   (MP_CLK),
                  .MP_CS_B                  (MP_CS_B),
                  .MP_ADDX                  (MP_ADDX),
                  .MP_DATA_TO_UART          (MP_DATA_TO_UART),
                  .MP_RD_B                  (MP_RD_B),
                  .MP_WR_B                  (MP_WR_B),
                  .XMIT_DONE                (XMIT_DONE),
                  .REC_DATA                 (REC_DATA),
                  .REC_READY                (REC_READY)
                  );


// Instantiate the Transmitter
U_XMIT I_U_XMIT_0 (
                  .UART_XMIT       (UART_XMIT_DATA),
                  .XMIT_DONE       (XMIT_DONE),
                  .SYS_CLK         (UART_CLK),
                  .SYS_RST_B       (SYS_RST_B),
                  .XMIT            (XMIT_START_PULSE),
                  .XMIT_DATA       (REG_XMIT_DAT)
                  );


// Instantiate the Receiver
U_REC I_U_REC_0 (
                .REC_DATA          (REC_DATA),
                .REC_READY         (REC_READY), 
                .SYS_RST_B         (SYS_RST_B),
                .SYS_CLK           (UART_CLK),
                .UART_DATA         (UART_REC_DATA)
                );

// Instantiate the Baud Rate Generator
BAUD I_BAUD_0 (
              .BAUD_CLK            (UART_CLK),
              .SYS_CLK             (SYS_CLK),
              .SYS_RST_B           (SYS_RST_B),		
              .BAUD_RATE_DIV       (BAUD_RATE_DIV)
              );
`endprotect

endmodule