mul8x8.rpt

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Project Information                                         c:\work\mul8x8.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/06/2007 20:28:21

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


MUL8X8


** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

mul8x8    EPF10K10LC84-3   16     16     0    0         0  %    169      29 %

User Pins:                 16     16     0  



Project Information                                         c:\work\mul8x8.rpt

** FILE HIERARCHY **



|lpm_mult:33|
|lpm_mult:33|multcore:mult_core|
|lpm_mult:33|multcore:mult_core|csa_add:padder|
|lpm_mult:33|multcore:mult_core|csa_add:padder|csa_cell:adder1|
|lpm_mult:33|multcore:mult_core|csa_add:padder|csa_cell:adder0|
|lpm_mult:33|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|
|lpm_mult:33|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder1|
|lpm_mult:33|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|
|lpm_mult:33|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|
|lpm_mult:33|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_cell:adder0|
|lpm_mult:33|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_add:sub_csa_add|
|lpm_mult:33|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_cell:adder0|
|lpm_mult:33|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|
|lpm_mult:33|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|
|lpm_mult:33|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:result_ext_latency_ffs|
|lpm_mult:33|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:carry_ext_latency_ffs|
|lpm_mult:33|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:oflow_ext_latency_ffs|
|lpm_mult:33|altshift:external_latency_ffs|


Device-Specific Information:                                c:\work\mul8x8.rpt
mul8x8

***** Logic for device 'mul8x8' compiled without errors.




Device: EPF10K10LC84-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f

                                                                         ^     
                                                                         C     
                      R                                   R  R  R  R     O     
                      E                                   E  E  E  E     N     
                      S              V                 G  S  S  S  S     F     
                      E     P        C                 N  E  E  E  E     _  ^  
                      R     R        C                 D  R  R  R  R  #  D  n  
                      V     O        I                 I  V  V  V  V  T  O  C  
                B  B  E  A  D  B  B  N  B  A  B  A  A  N  E  E  E  E  C  N  E  
                3  5  D  4  5  6  2  T  7  2  0  6  0  T  D  D  D  D  K  E  O  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
    ^DATA0 | 12                                                              74 | #TDO 
     ^DCLK | 13                                                              73 | PROD4 
      ^nCE | 14                                                              72 | PROD3 
      #TDI | 15                                                              71 | RESERVED 
     PROD6 | 16                                                              70 | RESERVED 
  RESERVED | 17                                                              69 | PROD7 
     PROD2 | 18                                                              68 | GNDINT 
     PROD8 | 19                                                              67 | RESERVED 
    VCCINT | 20                                                              66 | PROD11 
    PROD13 | 21                                                              65 | A7 
    PROD14 | 22                        EPF10K10LC84-3                        64 | PROD10 
    PROD12 | 23                                                              63 | VCCINT 
    PROD15 | 24                                                              62 | RESERVED 
     PROD9 | 25                                                              61 | PROD0 
    GNDINT | 26                                                              60 | PROD1 
  RESERVED | 27                                                              59 | RESERVED 
  RESERVED | 28                                                              58 | RESERVED 
  RESERVED | 29                                                              57 | #TMS 
  RESERVED | 30                                                              56 | #TRST 
    ^MSEL0 | 31                                                              55 | ^nSTATUS 
    ^MSEL1 | 32                                                              54 | RESERVED 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                V  ^  R  B  R  A  R  V  G  A  B  A  V  G  R  R  R  R  R  R  R  
                C  n  E  4  E  3  E  C  N  1  1  5  C  N  E  E  E  E  E  E  E  
                C  C  S     S     S  C  D           C  D  S  S  S  S  S  S  S  
                I  O  E     E     E  I  I           I  I  E  E  E  E  E  E  E  
                N  N  R     R     R  N  N           N  N  R  R  R  R  R  R  R  
                T  F  V     V     V  T  T           T  T  V  V  V  V  V  V  V  
                   I  E     E     E                       E  E  E  E  E  E  E  
                   G  D     D     D                       D  D  D  D  D  D  D  
                                                                               
                                                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                                c:\work\mul8x8.rpt
mul8x8

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A1       7/ 8( 87%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2       8/22( 36%)   
A2       2/ 8( 25%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2       4/22( 18%)   
A3       8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2       8/22( 36%)   
A4       8/ 8(100%)   1/ 8( 12%)   4/ 8( 50%)    0/2    0/2       9/22( 40%)   
A5       1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       2/22(  9%)   
A6       8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    0/2    0/2       7/22( 31%)   
A7       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    0/2    0/2       8/22( 36%)   
A8       8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    0/2    0/2      10/22( 45%)   
A10      8/ 8(100%)   2/ 8( 25%)   2/ 8( 25%)    0/2    0/2      10/22( 45%)   
A11      8/ 8(100%)   1/ 8( 12%)   2/ 8( 25%)    0/2    0/2       7/22( 31%)   
A12      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2       9/22( 40%)   
B1       8/ 8(100%)   1/ 8( 12%)   3/ 8( 37%)    0/2    0/2       9/22( 40%)   
B2       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    0/2    0/2       9/22( 40%)   
B3       8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2      11/22( 50%)   
B4       3/ 8( 37%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2       5/22( 22%)   
B5       8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    0/2    0/2       7/22( 31%)   
B6       8/ 8(100%)   0/ 8(  0%)   3/ 8( 37%)    0/2    0/2       9/22( 40%)   
B7       8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    0/2    0/2       9/22( 40%)   
B8       7/ 8( 87%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2       9/22( 40%)   
B9       8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2       8/22( 36%)   
B10      8/ 8(100%)   2/ 8( 25%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
B11      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2       7/22( 31%)   
B12      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2       9/22( 40%)