add123.rpt
来自「用VHDL语言实现通用计算器设计」· RPT 代码 · 共 629 行 · 第 1/2 页
RPT
629 行
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\work\add123.rpt
add123
** EQUATIONS **
adata0 : INPUT;
adata1 : INPUT;
adata2 : INPUT;
adata3 : INPUT;
adata4 : INPUT;
adata5 : INPUT;
adata6 : INPUT;
adata7 : INPUT;
bdata0 : INPUT;
bdata1 : INPUT;
bdata2 : INPUT;
bdata3 : INPUT;
bdata4 : INPUT;
bdata5 : INPUT;
bdata6 : INPUT;
bdata7 : INPUT;
cin : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC3_C13;
-- Node name is 'overflow'
-- Equation name is 'overflow', type is output
overflow = _LC1_C13;
-- Node name is 'result0'
-- Equation name is 'result0', type is output
result0 = _LC2_B2;
-- Node name is 'result1'
-- Equation name is 'result1', type is output
result1 = _LC8_B7;
-- Node name is 'result2'
-- Equation name is 'result2', type is output
result2 = _LC1_B7;
-- Node name is 'result3'
-- Equation name is 'result3', type is output
result3 = _LC7_B7;
-- Node name is 'result4'
-- Equation name is 'result4', type is output
result4 = _LC4_B7;
-- Node name is 'result5'
-- Equation name is 'result5', type is output
result5 = _LC5_C13;
-- Node name is 'result6'
-- Equation name is 'result6', type is output
result6 = _LC7_C13;
-- Node name is 'result7'
-- Equation name is 'result7', type is output
result7 = _LC4_C13;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry0' from file "addcore.tdf" line 308, column 64
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ001);
_EQ001 = adata0 & bdata0
# adata0 & cin
# bdata0 & cin;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ002);
_EQ002 = bdata1 & _LC1_B2
# adata1 & _LC1_B2
# adata1 & bdata1;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ003);
_EQ003 = bdata2 & _LC2_B7
# adata2 & _LC2_B7
# adata2 & bdata2;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ004);
_EQ004 = bdata3 & _LC5_B7
# adata3 & _LC5_B7
# adata3 & bdata3;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = LCELL( _EQ005);
_EQ005 = bdata4 & _LC3_B7
# adata4 & _LC3_B7
# adata4 & bdata4;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ006);
_EQ006 = bdata5 & _LC2_C13
# adata5 & _LC2_C13
# adata5 & bdata5;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = LCELL( _EQ007);
_EQ007 = bdata6 & _LC6_C13
# adata6 & _LC6_C13
# adata6 & bdata6;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry7' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = LCELL( _EQ008);
_EQ008 = adata7 & _LC8_C13
# bdata7 & _LC8_C13
# adata7 & bdata7;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|:148' from file "addcore.tdf" line 315, column 37
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ009);
_EQ009 = !adata0 & !bdata0 & cin
# !adata0 & bdata0 & !cin
# adata0 & bdata0 & cin
# adata0 & !bdata0 & !cin;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|:156' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ010);
_EQ010 = !adata1 & bdata1 & !_LC1_B2
# adata1 & !bdata1 & !_LC1_B2
# adata1 & bdata1 & _LC1_B2
# !adata1 & !bdata1 & _LC1_B2;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|:157' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = LCELL( _EQ011);
_EQ011 = !adata2 & bdata2 & !_LC2_B7
# adata2 & !bdata2 & !_LC2_B7
# adata2 & bdata2 & _LC2_B7
# !adata2 & !bdata2 & _LC2_B7;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|:158' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = LCELL( _EQ012);
_EQ012 = !adata3 & bdata3 & !_LC5_B7
# adata3 & !bdata3 & !_LC5_B7
# adata3 & bdata3 & _LC5_B7
# !adata3 & !bdata3 & _LC5_B7;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|:159' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = LCELL( _EQ013);
_EQ013 = !adata4 & bdata4 & !_LC3_B7
# adata4 & !bdata4 & !_LC3_B7
# adata4 & bdata4 & _LC3_B7
# !adata4 & !bdata4 & _LC3_B7;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|:160' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = LCELL( _EQ014);
_EQ014 = !adata5 & bdata5 & !_LC2_C13
# adata5 & !bdata5 & !_LC2_C13
# adata5 & bdata5 & _LC2_C13
# !adata5 & !bdata5 & _LC2_C13;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|:161' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = LCELL( _EQ015);
_EQ015 = !adata6 & bdata6 & !_LC6_C13
# adata6 & !bdata6 & !_LC6_C13
# adata6 & bdata6 & _LC6_C13
# !adata6 & !bdata6 & _LC6_C13;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|addcore:adder|:162' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = LCELL( _EQ016);
_EQ016 = adata7 & !bdata7 & !_LC8_C13
# !adata7 & bdata7 & !_LC8_C13
# adata7 & bdata7 & _LC8_C13
# !adata7 & !bdata7 & _LC8_C13;
-- Node name is '|add13:9|lpm_add_sub:lpm_add_sub_component|:150' from file "lpm_add_sub.tdf" line 704, column 91
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = LCELL( _EQ017);
_EQ017 = !adata7 & !bdata7 & _LC8_C13
# adata7 & bdata7 & !_LC8_C13;
Project Information c:\work\add123.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,929K
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