add12_inst.vhd

来自「用VHDL语言实现通用计算器设计」· VHDL 代码 · 共 9 行

add12_inst : add12 PORT MAP(
		dataa	 => dataa_sig,
		datab	 => datab_sig,
		cin	 => cin_sig,
		result	 => result_sig,
		cout	 => cout_sig,
		overflow	 => overflow_sig
	);