mul8x8.vhd

来自「用VHDL语言实现通用计算器设计」· VHDL 代码 · 共 15 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mul8x8 is
port(
A,B : in std_logic_vector( 7 downto 0);
PROD : out std_logic_vector(15 downto 0)
);
end mul8x8;

architecture SYNP of mul8x8 is
begin
PROD<=A*B;
end SYNP;