div1_inst.vhd

来自「用VHDL语言实现通用计算器设计」· VHDL 代码 · 共 7 行

div1_inst : div1 PORT MAP(
		numerator	 => numerator_sig,
		denominator	 => denominator_sig,
		quotient	 => quotient_sig,
		remainder	 => remainder_sig
	);