s_machine.vhd

用VHDL语言实现通用计算器设计

library ieee;
use ieee.std_logic_1164.all;
entity s_machine is
port(
	clk,reset :in std_logic;
	state_inputs :in std_logic_vector(0 to 1);
	comb_outputs :out std_logic_vector(0 to 1)
    );
end s_machine;

architecture behv of s_machine is
type states is (st0,st1,st2,st3);
signal current_state,next_state: states;

begin
reg:process(reset,clk)
begin
if reset ='1' then
current_state<=st0;
elsif clk='1'and clk'event then
current_state<=next_state;

end if;

end process reg;

com : process(current_state,state_inputs)
begin
case current_state is
when st0=>comb_outputs<="00";
	if state_inputs="00" then
       next_state<=st0;
    else
       next_state<=st1;
    end if;
 when st1=>comb_outputs<="01";
 if state_inputs="00" then
    next_state<=st1;
 else
    next_state<=st2;
 end if;
when st2=> comb_outputs<="10";
  if state_inputs="11" then
     next_state<=st2;
  else
     next_state<=st3;
  end if;
when st3=> comb_outputs<="11";
  if state_inputs="11" then
  next_state<=st3;
  else
  next_state<=st0;
end if;
end case;
end process com;
end behv;