numdecoder.rpt

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numdecoder

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        5         reset


Device-Specific Information:                            c:\work\numdecoder.rpt
numdecoder

** EQUATIONS **

inclk    : INPUT;
innum0   : INPUT;
innum1   : INPUT;
innum2   : INPUT;
innum3   : INPUT;
innum4   : INPUT;
innum5   : INPUT;
innum6   : INPUT;
innum7   : INPUT;
innum8   : INPUT;
innum9   : INPUT;
reset    : INPUT;

-- Node name is 'outflag' 
-- Equation name is 'outflag', type is output 
outflag  =  _LC1_C5;

-- Node name is 'outnum0' 
-- Equation name is 'outnum0', type is output 
outnum0  =  _LC2_C8;

-- Node name is 'outnum1' 
-- Equation name is 'outnum1', type is output 
outnum1  =  _LC5_C5;

-- Node name is 'outnum2' 
-- Equation name is 'outnum2', type is output 
outnum2  =  _LC4_C5;

-- Node name is 'outnum3' 
-- Equation name is 'outnum3', type is output 
outnum3  =  _LC7_C5;

-- Node name is 'reset~1' 
-- Equation name is 'reset~1', location is LC6_C5, type is buried.
-- synthesized logic cell 
!_LC6_C5 = _LC6_C5~NOT;
_LC6_C5~NOT = LCELL(!reset);

-- Node name is ':13' 
-- Equation name is '_LC7_C5', type is buried 
_LC7_C5  = DFFE( _EQ001, GLOBAL( inclk), GLOBAL(!reset),  VCC,  VCC);
  _EQ001 = !_LC2_C10 &  _LC3_C5 &  _LC7_C5
         # !_LC2_C10 &  _LC3_C5 &  _LC7_C2;

-- Node name is ':15' 
-- Equation name is '_LC4_C5', type is buried 
_LC4_C5  = DFFE( _EQ002, GLOBAL( inclk), GLOBAL(!reset),  VCC,  VCC);
  _EQ002 =  _LC2_C10 &  _LC3_C5
         #  _LC3_C5 &  _LC4_C5 & !_LC7_C2;

-- Node name is ':17' 
-- Equation name is '_LC5_C5', type is buried 
_LC5_C5  = DFFE( _EQ003, GLOBAL( inclk), GLOBAL(!reset),  VCC,  VCC);
  _EQ003 =  _LC1_C8 &  _LC4_C8
         #  _LC1_C8 &  _LC5_C8
         #  _LC1_C8 &  _LC2_C5;

-- Node name is ':19' 
-- Equation name is '_LC2_C8', type is buried 
_LC2_C8  = DFFE( _EQ004, GLOBAL( inclk), GLOBAL(!reset),  VCC,  VCC);
  _EQ004 = !innum0 &  innum1 & !_LC6_C8
         # !innum0 &  _LC8_C8
         #  innum1 &  _LC8_C8
         #  _LC6_C8 &  _LC8_C8;

-- Node name is ':21' 
-- Equation name is '_LC1_C5', type is buried 
_LC1_C5  = DFFE( _EQ005, GLOBAL( inclk),  VCC,  VCC, !_LC6_C5);
  _EQ005 = !_LC3_C5
         #  _LC2_C10
         #  _LC7_C2;

-- Node name is '~276~1' 
-- Equation name is '~276~1', location is LC7_C8, type is buried.
-- synthesized logic cell 
_LC7_C8  = LCELL( _EQ006);
  _EQ006 = !innum0 & !innum1;

-- Node name is '~276~2' 
-- Equation name is '~276~2', location is LC3_C8, type is buried.
-- synthesized logic cell 
_LC3_C8  = LCELL( _EQ007);
  _EQ007 = !innum2 & !innum3 &  _LC7_C8;

-- Node name is '~276~3' 
-- Equation name is '~276~3', location is LC6_C2, type is buried.
-- synthesized logic cell 
_LC6_C2  = LCELL( _EQ008);
  _EQ008 = !innum4 & !innum5 & !innum6 &  _LC3_C8;

-- Node name is '~276~4' 
-- Equation name is '~276~4', location is LC8_C2, type is buried.
-- synthesized logic cell 
_LC8_C2  = LCELL( _EQ009);
  _EQ009 = !innum7 &  _LC6_C2;

-- Node name is ':300' 
-- Equation name is '_LC2_C2', type is buried 
_LC2_C2  = LCELL( _EQ010);
  _EQ010 =  innum7 & !innum8 & !innum9 &  _LC6_C2;

-- Node name is '~324~1' 
-- Equation name is '~324~1', location is LC3_C2, type is buried.
-- synthesized logic cell 
_LC3_C2  = LCELL( _EQ011);
  _EQ011 =  _LC5_C2
         # !innum6;

-- Node name is ':324' 
-- Equation name is '_LC7_C10', type is buried 
!_LC7_C10 = _LC7_C10~NOT;
_LC7_C10~NOT = LCELL( _EQ012);
  _EQ012 =  _LC3_C2
         #  innum4
         # !_LC3_C8
         #  innum5;

-- Node name is ':348' 
-- Equation name is '_LC6_C10', type is buried 
_LC6_C10 = LCELL( _EQ013);
  _EQ013 = !innum4 &  innum5 & !_LC1_C11 &  _LC3_C8;

-- Node name is ':372' 
-- Equation name is '_LC5_C10', type is buried 
!_LC5_C10 = _LC5_C10~NOT;
_LC5_C10~NOT = LCELL( _EQ014);
  _EQ014 =  _LC1_C11
         #  innum5
         # !innum4
         # !_LC3_C8;

-- Node name is ':396' 
-- Equation name is '_LC5_C8', type is buried 
_LC5_C8  = LCELL( _EQ015);
  _EQ015 = !innum2 &  innum3 & !_LC4_C2 &  _LC7_C8;

-- Node name is ':420' 
-- Equation name is '_LC4_C8', type is buried 
!_LC4_C8 = _LC4_C8~NOT;
_LC4_C8~NOT = LCELL( _EQ016);
  _EQ016 =  _LC4_C2
         #  innum3
         # !innum2
         # !_LC7_C8;

-- Node name is '~468~1' 
-- Equation name is '~468~1', location is LC5_C2, type is buried.
-- synthesized logic cell 
_LC5_C2  = LCELL( _EQ017);
  _EQ017 =  innum9
         #  innum8
         #  innum7;

-- Node name is '~468~2' 
-- Equation name is '~468~2', location is LC4_C2, type is buried.
-- synthesized logic cell 
!_LC4_C2 = _LC4_C2~NOT;
_LC4_C2~NOT = LCELL( _EQ018);
  _EQ018 = !innum4 & !innum5 & !innum6 & !_LC5_C2;

-- Node name is '~468~3' 
-- Equation name is '~468~3', location is LC6_C8, type is buried.
-- synthesized logic cell 
!_LC6_C8 = _LC6_C8~NOT;
_LC6_C8~NOT = LCELL( _EQ019);
  _EQ019 = !innum2 & !innum3 & !_LC4_C2;

-- Node name is '~468~4' 
-- Equation name is '~468~4', location is LC1_C11, type is buried.
-- synthesized logic cell 
!_LC1_C11 = _LC1_C11~NOT;
_LC1_C11~NOT = LCELL( _EQ020);
  _EQ020 = !innum6 & !_LC5_C2;

-- Node name is '~473~1' 
-- Equation name is '~473~1', location is LC4_C10, type is buried.
-- synthesized logic cell 
!_LC4_C10 = _LC4_C10~NOT;
_LC4_C10~NOT = LCELL( _EQ021);
  _EQ021 =  _LC7_C10
         #  _LC2_C2;

-- Node name is '~473~2' 
-- Equation name is '~473~2', location is LC3_C5, type is buried.
-- synthesized logic cell 
_LC3_C5  = LCELL( _EQ022);
  _EQ022 =  _LC1_C8 & !_LC4_C8 & !_LC5_C8;

-- Node name is '~506~1' 
-- Equation name is '~506~1', location is LC1_C8, type is buried.
-- synthesized logic cell 
_LC1_C8  = LCELL( _EQ023);
  _EQ023 =  _LC6_C8
         #  innum0 &  innum1
         # !innum0 & !innum1;

-- Node name is ':530' 
-- Equation name is '_LC2_C5', type is buried 
_LC2_C5  = LCELL( _EQ024);
  _EQ024 = !_LC3_C10 & !_LC4_C10
         # !_LC3_C10 &  _LC5_C5 & !_LC7_C2;

-- Node name is ':551' 
-- Equation name is '_LC1_C2', type is buried 
_LC1_C2  = LCELL( _EQ025);
  _EQ025 = !innum8 &  innum9 &  _LC8_C2
         #  innum9 &  _LC2_C8
         # !innum8 &  _LC2_C8
         #  _LC2_C8 & !_LC8_C2;

-- Node name is ':555' 
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = LCELL( _EQ026);
  _EQ026 =  _LC6_C10
         #  _LC2_C2 & !_LC7_C10
         #  _LC1_C2 & !_LC7_C10;

-- Node name is ':569' 
-- Equation name is '_LC8_C8', type is buried 
_LC8_C8  = LCELL( _EQ027);
  _EQ027 = !_LC4_C8 &  _LC5_C8
         #  _LC1_C10 & !_LC4_C8 & !_LC5_C10;

-- Node name is '~603~1' 
-- Equation name is '~603~1', location is LC3_C10, type is buried.
-- synthesized logic cell 
!_LC3_C10 = _LC3_C10~NOT;
_LC3_C10~NOT = LCELL( _EQ028);
  _EQ028 = !_LC5_C10 & !_LC6_C10;

-- Node name is '~603~2' 
-- Equation name is '~603~2', location is LC7_C2, type is buried.
-- synthesized logic cell 
!_LC7_C2 = _LC7_C2~NOT;
_LC7_C2~NOT = LCELL( _EQ029);
  _EQ029 =  innum7
         # !_LC6_C2
         # !innum8 & !innum9
         #  innum8 &  innum9;

-- Node name is '~603~3' 
-- Equation name is '~603~3', location is LC2_C10, type is buried.
-- synthesized logic cell 
_LC2_C10 = LCELL( _EQ030);
  _EQ030 =  _LC5_C10
         #  _LC6_C10
         #  _LC7_C10
         #  _LC2_C2;



Project Information                                     c:\work\numdecoder.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,566K