div1.vhd

用VHDL语言实现通用计算器设计

-- megafunction wizard: %LPM_DIVIDE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: divide 

-- ============================================================
-- File Name: div1.vhd
-- Megafunction Name(s):
-- 			divide
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************


--	Copyright (C) 1988-2000 Altera Corporation

--	Any megafunction design, and related net list (encrypted or decrypted),
--	support information, device programming or simulation file, and any other
--	associated documentation or information provided by Altera or a partner
--	under Altera's Megafunction Partnership Program may be used only to
--	program PLD devices (but not masked PLD devices) from Altera.  Any other
--	use of such megafunction design, net list, support information, device
--	programming or simulation file, or any other related documentation or
--	information is prohibited for any other purpose, including, but not
--	limited to modification, reverse engineering, de-compiling, or use with
--	any other silicon devices, unless such use is explicitly licensed under
--	a separate agreement with Altera or a megafunction partner.  Title to
--	the intellectual property, including patents, copyrights, trademarks,
--	trade secrets, or maskworks, embodied in any such megafunction design,
--	net list, support information, device programming or simulation file, or
--	any other related documentation or information provided by Altera or a
--	megafunction partner, remains with Altera, the megafunction partner, or
--	their respective licensors.  No other licenses, including any licenses
--	needed under any third party's intellectual property, are provided herein.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY div1 IS
	PORT
	(
		numerator		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		denominator		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		quotient		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		remainder		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
END div1;


ARCHITECTURE SYN OF div1 IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);



	COMPONENT divide
	GENERIC (
		width_n		: NATURAL;
		width_d		: NATURAL;
		width_q		: NATURAL;
		width_r		: NATURAL;
		width_d_min		: NATURAL;
		lpm_pipeline		: NATURAL;
		pipeline_delay		: NATURAL
	);
	PORT (
			numerator	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			remainder	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
			denominator	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
			quotient	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	remainder    <= sub_wire0(3 DOWNTO 0);
	quotient    <= sub_wire1(7 DOWNTO 0);

	divide_component : divide
	GENERIC MAP (
		WIDTH_N => 8,
		WIDTH_D => 4,
		WIDTH_Q => 8,
		WIDTH_R => 4,
		WIDTH_D_MIN => 1,
		LPM_PIPELINE => 0,
		PIPELINE_DELAY => 0
	)
	PORT MAP (
		numerator => numerator,
		denominator => denominator,
		remainder => sub_wire0,
		quotient => sub_wire1
	);



END SYN;

-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: USER_WIDTH_D_MIN NUMERIC "1"
-- Retrieval info: PRIVATE: USE_DEF_WIDTH_D_MIN NUMERIC "1"
-- Retrieval info: PRIVATE: USE_NO_PIPELINE NUMERIC "1"
-- Retrieval info: PRIVATE: USE_DEF_PIPELINE_DELAY NUMERIC "1"
-- Retrieval info: PRIVATE: STAGE_POS_CUR_SEL NUMERIC "0"
-- Retrieval info: CONSTANT: WIDTH_N NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_D NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_Q NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_R NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_D_MIN NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: CONSTANT: PIPELINE_DELAY NUMERIC "0"
-- Retrieval info: USED_PORT: numerator 0 0 8 0 INPUT NODEFVAL numerator[7..0]
-- Retrieval info: USED_PORT: denominator 0 0 4 0 INPUT NODEFVAL denominator[3..0]
-- Retrieval info: USED_PORT: quotient 0 0 8 0 OUTPUT NODEFVAL quotient[7..0]
-- Retrieval info: USED_PORT: remainder 0 0 4 0 OUTPUT NODEFVAL remainder[3..0]
-- Retrieval info: CONNECT: @numerator 0 0 8 0 numerator 0 0 8 0
-- Retrieval info: CONNECT: @denominator 0 0 4 0 denominator 0 0 4 0
-- Retrieval info: CONNECT: quotient 0 0 8 0 @quotient 0 0 8 0
-- Retrieval info: CONNECT: remainder 0 0 4 0 @remainder 0 0 4 0