half_adder.qsf

用VHDL语言实现半加器。已经通过编译和仿真

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		half_adder_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:07:47  DECEMBER 29, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP1"
set_global_assignment -name VHDL_FILE half_adder.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE half_adder.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_105 -to a
set_location_assignment PIN_104 -to b
set_location_assignment PIN_132 -to co
set_location_assignment PIN_133 -to s

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY half_adder

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C12Q240C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL VCS

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE ON
set_global_assignment -name VECTOR_INPUT_SOURCE half_adder.vwf
set_global_assignment -name SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION half_adder.saf

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------

set_global_assignment -name VHDL_FILE ../../11/Vhdl1.vhd
set_location_assignment PIN_162 -to VGA[0]
set_location_assignment PIN_161 -to VGA[1]
set_location_assignment PIN_164 -to VGA[2]
set_location_assignment PIN_163 -to VGA[3]
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"