half_adder.fit.eqn

用VHDL语言实现半加器。已经通过编译和仿真

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L6 is s~2 at LC_X52_Y2_N4
--operation mode is normal

A1L6 = a $ b;


--d is d at LC_X52_Y2_N2
--operation mode is normal

d = a & b;


--b is b at PIN_104
--operation mode is input

b = INPUT();


--a is a at PIN_105
--operation mode is input

a = INPUT();


--s is s at PIN_133
--operation mode is output

s = OUTPUT(A1L6);


--co is co at PIN_132
--operation mode is output

co = OUTPUT(d);


--VGA[0] is VGA[0] at PIN_162
--operation mode is output

VGA[0] = OUTPUT(VCC);


--VGA[1] is VGA[1] at PIN_161
--operation mode is output

VGA[1] = OUTPUT(GND);


--VGA[2] is VGA[2] at PIN_164
--operation mode is output

VGA[2] = OUTPUT(GND);


--VGA[3] is VGA[3] at PIN_163
--operation mode is output

VGA[3] = OUTPUT(GND);