prev_cmp_counter.tan.qmsg

带清零和重置功能的十进制计数器

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 10 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\] register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_trigger_address_var\[4\] 141.3 MHz 7.077 ns Internal " "Info: Clock \"clk\" has Internal fmax of 141.3 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_trigger_address_var\[4\]\" (period= 7.077 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.816 ns + Longest register register " "Info: + Longest register to register delay is 6.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\] 1 REG LC_X39_Y15_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X39_Y15_N2; Fanout = 5; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.590 ns) 1.143 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~93 2 COMB LC_X39_Y15_N6 1 " "Info: 2: + IC(0.553 ns) + CELL(0.590 ns) = 1.143 ns; Loc. = LC_X39_Y15_N6; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~93'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.143 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~93 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.442 ns) 2.811 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~94 3 COMB LC_X38_Y16_N8 17 " "Info: 3: + IC(1.226 ns) + CELL(0.442 ns) = 2.811 ns; Loc. = LC_X38_Y16_N8; Fanout = 17; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~94'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.668 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~93 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.442 ns) 3.696 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|segment_shift_var~46 4 COMB LC_X38_Y16_N5 15 " "Info: 4: + IC(0.443 ns) + CELL(0.442 ns) = 3.696 ns; Loc. = LC_X38_Y16_N5; Fanout = 15; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|segment_shift_var~46'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.885 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~46 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.292 ns) 5.308 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count~89 5 COMB LC_X38_Y14_N2 2 " "Info: 5: + IC(1.320 ns) + CELL(0.292 ns) = 5.308 ns; Loc. = LC_X38_Y14_N2; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count~89'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.612 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~46 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~89 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.309 ns) 6.816 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_trigger_address_var\[4\] 6 REG LC_X38_Y15_N6 2 " "Info: 6: + IC(1.199 ns) + CELL(0.309 ns) = 6.816 ns; Loc. = LC_X38_Y15_N6; Fanout = 2; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_trigger_address_var\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~89 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.075 ns ( 30.44 % ) " "Info: Total cell delay = 2.075 ns ( 30.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.741 ns ( 69.56 % ) " "Info: Total interconnect delay = 4.741 ns ( 69.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.816 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~93 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~46 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~89 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.816 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~93 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~46 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~89 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] {} } { 0.000ns 0.553ns 1.226ns 0.443ns 1.320ns 1.199ns } { 0.000ns 0.590ns 0.442ns 0.442ns 0.292ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.178 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 191 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 191; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.711 ns) 3.178 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_trigger_address_var\[4\] 2 REG LC_X38_Y15_N6 2 " "Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X38_Y15_N6; Fanout = 2; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_trigger_address_var\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.60 % ) " "Info: Total cell delay = 2.180 ns ( 68.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 31.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 31.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.178 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 191 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 191; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.711 ns) 3.178 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\] 2 REG LC_X39_Y15_N2 5 " "Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X39_Y15_N2; Fanout = 5; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.60 % ) " "Info: Total cell delay = 2.180 ns ( 68.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 31.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 31.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.816 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~93 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~46 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~89 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.816 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~93 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~94 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~46 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~89 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] {} } { 0.000ns 0.553ns 1.226ns 0.443ns 1.320ns 1.199ns } { 0.000ns 0.590ns 0.442ns 0.442ns 0.292ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_trigger_address_var[4] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { clk sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.178 ns" { clk {} clk~out0 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} } { 0.000ns 0.000ns 0.998ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\] register sld_hub:sld_hub_inst\|hub_tdo_reg 96.99 MHz 10.31 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 96.99 MHz between source register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 10.31 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.894 ns + Longest register register " "Info: + Longest register to register delay is 4.894 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\] 1 REG LC_X38_Y10_N8 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y10_N8; Fanout = 20; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.214 ns) + CELL(0.442 ns) 1.656 ns sld_hub:sld_hub_inst\|hub_tdo_reg~611 2 COMB LC_X36_Y10_N4 2 " "Info: 2: + IC(1.214 ns) + CELL(0.442 ns) = 1.656 ns; Loc. = LC_X36_Y10_N4; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~611'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.656 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] sld_hub:sld_hub_inst|hub_tdo_reg~611 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.109 ns) + CELL(0.442 ns) 3.207 ns sld_hub:sld_hub_inst\|hub_tdo_reg~613 3 COMB LC_X36_Y10_N9 1 " "Info: 3: + IC(1.109 ns) + CELL(0.442 ns) = 3.207 ns; Loc. = LC_X36_Y10_N9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~613'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~611 sld_hub:sld_hub_inst|hub_tdo_reg~613 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.459 ns) + CELL(0.292 ns) 3.958 ns sld_hub:sld_hub_inst\|hub_tdo_reg~616 4 COMB LC_X36_Y10_N2 1 " "Info: 4: + IC(0.459 ns) + CELL(0.292 ns) = 3.958 ns; Loc. = LC_X36_Y10_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~616'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.751 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~613 sld_hub:sld_hub_inst|hub_tdo_reg~616 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.458 ns) + CELL(0.478 ns) 4.894 ns sld_hub:sld_hub_inst\|hub_tdo_reg 5 REG LC_X36_Y10_N3 1 " "Info: 5: + IC(0.458 ns) + CELL(0.478 ns) = 4.894 ns; Loc. = LC_X36_Y10_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.936 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~616 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.654 ns ( 33.80 % ) " "Info: Total cell delay = 1.654 ns ( 33.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.240 ns ( 66.20 % ) " "Info: Total interconnect delay = 3.240 ns ( 66.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.894 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] sld_hub:sld_hub_inst|hub_tdo_reg~611 sld_hub:sld_hub_inst|hub_tdo_reg~613 sld_hub:sld_hub_inst|hub_tdo_reg~616 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.894 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] {} sld_hub:sld_hub_inst|hub_tdo_reg~611 {} sld_hub:sld_hub_inst|hub_tdo_reg~613 {} sld_hub:sld_hub_inst|hub_tdo_reg~616 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.214ns 1.109ns 0.459ns 0.458ns } { 0.000ns 0.442ns 0.442ns 0.292ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.283 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 244 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 244; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.572 ns) + CELL(0.711 ns) 5.283 ns sld_hub:sld_hub_inst\|hub_tdo_reg 2 REG LC_X36_Y10_N3 1 " "Info: 2: + IC(4.572 ns) + CELL(0.711 ns) = 5.283 ns; Loc. = LC_X36_Y10_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.46 % ) " "Info: Total cell delay = 0.711 ns ( 13.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.572 ns ( 86.54 % ) " "Info: Total interconnect delay = 4.572 ns ( 86.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.572ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.283 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 244 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 244; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.572 ns) + CELL(0.711 ns) 5.283 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\] 2 REG LC_X38_Y10_N8 20 " "Info: 2: + IC(4.572 ns) + CELL(0.711 ns) = 5.283 ns; Loc. = LC_X38_Y10_N8; Fanout = 20; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.46 % ) " "Info: Total cell delay = 0.711 ns ( 13.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.572 ns ( 86.54 % ) " "Info: Total interconnect delay = 4.572 ns ( 86.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] {} } { 0.000ns 4.572ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.572ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] {} } { 0.000ns 4.572ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } } { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.894 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] sld_hub:sld_hub_inst|hub_tdo_reg~611 sld_hub:sld_hub_inst|hub_tdo_reg~613 sld_hub:sld_hub_inst|hub_tdo_reg~616 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.894 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] {} sld_hub:sld_hub_inst|hub_tdo_reg~611 {} sld_hub:sld_hub_inst|hub_tdo_reg~613 {} sld_hub:sld_hub_inst|hub_tdo_reg~616 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.214ns 1.109ns 0.459ns 0.458ns } { 0.000ns 0.442ns 0.442ns 0.292ns 0.478ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.572ns } { 0.000ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] {} } { 0.000ns 4.572ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}