counter.tan.qmsg

带清零和重置功能的十进制计数器

{ "Info" "ITDB_TSU_RESULT" "q10\[0\] clr clk 9.832 ns register " "Info: tsu for register \"q10\[0\]\" (data pin = \"clr\", clock pin = \"clk\") is 9.832 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.906 ns + Longest pin register " "Info: + Longest pin to register delay is 12.906 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clr 1 PIN PIN_104 34 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_104; Fanout = 34; PIN Node = 'clr'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.185 ns) + CELL(0.590 ns) 10.250 ns q10\[0\]~1901 2 COMB LC_X31_Y10_N4 32 " "Info: 2: + IC(8.185 ns) + CELL(0.590 ns) = 10.250 ns; Loc. = LC_X31_Y10_N4; Fanout = 32; COMB Node = 'q10\[0\]~1901'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.775 ns" { clr q10[0]~1901 } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.789 ns) + CELL(0.867 ns) 12.906 ns q10\[0\] 3 REG LC_X27_Y12_N3 36 " "Info: 3: + IC(1.789 ns) + CELL(0.867 ns) = 12.906 ns; Loc. = LC_X27_Y12_N3; Fanout = 36; REG Node = 'q10\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { q10[0]~1901 q10[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.932 ns ( 22.72 % ) " "Info: Total cell delay = 2.932 ns ( 22.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.974 ns ( 77.28 % ) " "Info: Total interconnect delay = 9.974 ns ( 77.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.906 ns" { clr q10[0]~1901 q10[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.906 ns" { clr {} clr~out0 {} q10[0]~1901 {} q10[0] {} } { 0.000ns 0.000ns 8.185ns 1.789ns } { 0.000ns 1.475ns 0.590ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.111 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 191 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 191; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns q10\[0\] 2 REG LC_X27_Y12_N3 36 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X27_Y12_N3; Fanout = 36; REG Node = 'q10\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { clk q10[0] } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk q10[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk {} clk~out0 {} q10[0] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.906 ns" { clr q10[0]~1901 q10[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.906 ns" { clr {} clr~out0 {} q10[0]~1901 {} q10[0] {} } { 0.000ns 0.000ns 8.185ns 1.789ns } { 0.000ns 1.475ns 0.590ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk q10[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk {} clk~out0 {} q10[0] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Q\[3\] q10\[3\] 10.059 ns register " "Info: tco from clock \"clk\" to destination pin \"Q\[3\]\" through register \"q10\[3\]\" is 10.059 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.111 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 191 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 191; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns q10\[3\] 2 REG LC_X27_Y12_N2 6 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X27_Y12_N2; Fanout = 6; REG Node = 'q10\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { clk q10[3] } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 70.07 % ) " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns ( 29.93 % ) " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk q10[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk {} clk~out0 {} q10[3] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.724 ns + Longest register pin " "Info: + Longest register to pin delay is 6.724 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q10\[3\] 1 REG LC_X27_Y12_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y12_N2; Fanout = 6; REG Node = 'q10\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q10[3] } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(2.124 ns) 6.724 ns Q\[3\] 2 PIN PIN_135 0 " "Info: 2: + IC(4.600 ns) + CELL(2.124 ns) = 6.724 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'Q\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.724 ns" { q10[3] Q[3] } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 31.59 % ) " "Info: Total cell delay = 2.124 ns ( 31.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns ( 68.41 % ) " "Info: Total interconnect delay = 4.600 ns ( 68.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.724 ns" { q10[3] Q[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.724 ns" { q10[3] {} Q[3] {} } { 0.000ns 4.600ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.111 ns" { clk q10[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.111 ns" { clk {} clk~out0 {} q10[3] {} } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.724 ns" { q10[3] Q[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.724 ns" { q10[3] {} Q[3] {} } { 0.000ns 4.600ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "en co 14.830 ns Longest " "Info: Longest tpd from source pin \"en\" to destination pin \"co\" is 14.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns en 1 PIN PIN_105 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_105; Fanout = 3; PIN Node = 'en'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.000 ns) + CELL(0.292 ns) 8.767 ns co~0 2 COMB LC_X31_Y10_N0 2 " "Info: 2: + IC(7.000 ns) + CELL(0.292 ns) = 8.767 ns; Loc. = LC_X31_Y10_N0; Fanout = 2; COMB Node = 'co~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.292 ns" { en co~0 } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.939 ns) + CELL(2.124 ns) 14.830 ns co 3 PIN PIN_136 0 " "Info: 3: + IC(3.939 ns) + CELL(2.124 ns) = 14.830 ns; Loc. = PIN_136; Fanout = 0; PIN Node = 'co'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.063 ns" { co~0 co } "NODE_NAME" } } { "counter.vhd" "" { Text "E:/test_20/t1/counter.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.891 ns ( 26.24 % ) " "Info: Total cell delay = 3.891 ns ( 26.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.939 ns ( 73.76 % ) " "Info: Total interconnect delay = 10.939 ns ( 73.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.830 ns" { en co~0 co } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.830 ns" { en {} en~out0 {} co~0 {} co {} } { 0.000ns 0.000ns 7.000ns 3.939ns } { 0.000ns 1.475ns 0.292ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}