📄 闹钟程序.txt
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.P_ALARM.ALL;
ENTITY ALARM_CLOCK IS
PORT(YES,CLK,ALARM_BUTTON,TIME_BUTTON,RESET:STD_LOGIC;
SOUND_ALARM:OUT STD_LOGIC;
LEDW:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SEG7:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ALARM_CLOCK;
ARCHITECTURE ONE OF ALARM_CLOCK IS
COMPONENT KEYBUFFER
PORT(KEY:IN STD_LOGIC;
CLK:IN STD_LOGIC;
RESET:IN STD_LOGIC;
KEYNUM:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
NEW_TIME:OUT T_CLOCK_TIME);
END COMPONENT;
COMPONENT DIVIDER
PORT(CLK_IN:STD_LOGIC;
RESET:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC);
END COMPONENT;
COMPONENT CONTROL
PORT(KEY:IN STD_LOGIC;
ALARM_BUTTON:IN STD_LOGIC;
TIME_BUTTON:IN STD_LOGIC;
CLK:IN STD_LOGIC;
RESET:IN STD_LOGIC;
LOAD_NEW_A:OUT STD_LOGIC;
LOAD_NEW_C:OUT STD_LOGIC;
SHOW_NEW_TIME:OUT STD_LOGIC;
SHOW_A:OUT STD_LOGIC);
END COMPONENT;
COMPONENT COUNTER
PORT(NEW_CURRENT_TIME:IN T_CLOCK_TIME;
LOAD_NEW_C,CLK,RESET:IN STD_LOGIC;
CURRENT_TIME:OUT T_CLOCK_TIME);
END COMPONENT;
COMPONENT REG
PORT(NEW_ALARM_TIME:IN T_CLOCK_TIME;
LOAD_NEW_A:IN STD_LOGIC;
CLK:IN STD_LOGIC;
RESET:IN STD_LOGIC;
ALARM_TIME:OUT T_CLOCK_TIME);
END COMPONENT;
COMPONENT DRIVER
PORT(KEYNUM:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK:IN STD_LOGIC;
ALARM_TIME:IN T_CLOCK_TIME;
CURRENT_TIME:IN T_CLOCK_TIME;
NEW_TIME:IN T_CLOCK_TIME;
SHOW_NEW_TIME:IN STD_LOGIC;
SHOW_A:IN STD_LOGIC;
SOUND_ALARM:OUT STD_LOGIC;
LEDW:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SEG7:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
SIGNAL TMP0,TMP3,TMP4,TMP5,TMP6:STD_LOGIC;
SIGNAL TMP2,TMP7,TMP8:T_CLOCK_TIME;
SIGNAL TMP1:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
U1:KEYBUFFER PORT MAP (YES,TMP0,RESET,TMP1,TMP2);
U2:DIVIDER PORT MAP (CLK,RESET,TMP0);
U3:CONTROL PORT MAP (YES,ALARM_BUTTON,TIME_BUTTON,CLK,RESET,TMP3,TMP4,TMP5,TMP6);
U4:COUNTER PORT MAP (TMP2,TMP4,TMP0,RESET,TMP7);
U5:REG PORT MAP (TMP2,TMP3,CLK,RESET,TMP8);
U6:DRIVER PORT MAP (TMP1,CLK,TMP8,TMP7,TMP2,TMP5,TMP6,SOUND_ALARM,LEDW,SEG7);
END ONE;
-------------------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE P_ALARM IS
SUBTYPE T_DIGITAL IS INTEGER RANGE 0 TO 9;
SUBTYPE T_SHORT IS INTEGER RANGE 0 TO 65535;
TYPE T_CLOCK_TIME IS ARRAY (5 DOWNTO 0) OF T_DIGITAL;
TYPE T_DISPLAY IS ARRAY (5 DOWNTO 0) OF T_DIGITAL;
END PACKAGE P_ALARM;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY CONTROL IS
PORT(KEY:IN STD_LOGIC;
ALARM_BUTTON:IN STD_LOGIC;
TIME_BUTTON:IN STD_LOGIC;
CLK:IN STD_LOGIC;
RESET:IN STD_LOGIC;
LOAD_NEW_A:OUT STD_LOGIC;
LOAD_NEW_C:OUT STD_LOGIC;
SHOW_NEW_TIME:OUT STD_LOGIC;
SHOW_A:OUT STD_LOGIC);
END ENTITY CONTROL;
ARCHITECTURE ART OF CONTROL IS
TYPE T_STATE IS(S0,S1,S2,S3,S4);
CONSTANT KEY_TIMEOUT:T_SHORT:=500;
CONSTANT SHOW_ALARM_TIMEOUT:T_SHORT:=500;
SIGNAL CURR_STATE:T_STATE;
SIGNAL NEXT_STATE:T_STATE;
SIGNAL COUNTER_K:T_SHORT;
SIGNAL ENABLE_COUNT_K:STD_LOGIC;
SIGNAL COUNT_K_END:STD_LOGIC;
SIGNAL COUNTER_A:T_SHORT;
SIGNAL ENABLE_COUNT_A:STD_LOGIC;
SIGNAL COUNT_A_END:STD_LOGIC;
BEGIN
PROCESS(CLK,RESET) IS
BEGIN
IF RESET='1' THEN
CURR_STATE<=S0;
ELSIF RISING_EDGE(CLK)THEN
CURR_STATE<=NEXT_STATE;
END IF;
END PROCESS;
PROCESS(KEY,ALARM_BUTTON,TIME_BUTTON,CURR_STATE,COUNT_A_END,COUNT_K_END)
BEGIN
NEXT_STATE<=CURR_STATE;
LOAD_NEW_A<='0';
LOAD_NEW_C<='0';
SHOW_A<='0';
SHOW_NEW_TIME<='0';
ENABLE_COUNT_K<='0';
ENABLE_COUNT_A<='0';
CASE CURR_STATE IS
WHEN S0=>IF (KEY='1') THEN
NEXT_STATE<=S1;
SHOW_NEW_TIME<='1';
ELSIF (ALARM_BUTTON='1') THEN
NEXT_STATE<=S4;
SHOW_A<='1';
ELSE
NEXT_STATE<=S0;
END IF;
WHEN S1=>IF (KEY='1') THEN
NEXT_STATE<=S1;
ELSIF (ALARM_BUTTON='1') THEN
NEXT_STATE<=S2;
LOAD_NEW_A<='1';
ELSIF (TIME_BUTTON='1') THEN
NEXT_STATE<=S3;
LOAD_NEW_C<='1';
ELSE
IF (COUNT_K_END='1') THEN
NEXT_STATE<=S0;
ELSE
NEXT_STATE<=S1;
END IF;
ENABLE_COUNT_K<='1';
END IF;
SHOW_NEW_TIME<='1';
WHEN S2=>IF (ALARM_BUTTON='1') THEN
NEXT_STATE<=S2;
LOAD_NEW_A<='1';
ELSE
NEXT_STATE<=S0;
END IF;
WHEN S3=>IF (TIME_BUTTON='1') THEN
NEXT_STATE<=S3;
LOAD_NEW_C<='1';
ELSE
NEXT_STATE<=S0;--
END IF;
WHEN S4=>IF (KEY='1') THEN
NEXT_STATE<=S1;
ELSE
--NEXT_STATE<=S4;
IF (COUNT_A_END='1') THEN
NEXT_STATE<=S0;
ELSE
NEXT_STATE<=S4;
SHOW_A<='1';
END IF;
ENABLE_COUNT_A<='1';
END IF;
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
COUNT_KEY:PROCESS(ENABLE_COUNT_K,CLK) IS
BEGIN
IF (ENABLE_COUNT_K='0') THEN
COUNTER_K<=0;
COUNT_K_END<='0';
ELSIF (RISING_EDGE(CLK)) THEN
IF (COUNTER_K>=KEY_TIMEOUT) THEN
COUNT_K_END<='1';
ELSE
COUNTER_K<=COUNTER_K+1;
END IF;
END IF;
END PROCESS;
COUNT_ALARM:PROCESS(ENABLE_COUNT_A,CLK) IS
BEGIN
IF(ENABLE_COUNT_A='0') THEN
COUNTER_A<=0;
COUNT_A_END<='0';
ELSIF RISING_EDGE(CLK) THEN
IF (COUNTER_A>=SHOW_ALARM_TIMEOUT) THEN
COUNT_A_END<='1';
ELSE
COUNTER_A<=COUNTER_A+1;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART;
--------------------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY COUNTER IS
PORT(NEW_CURRENT_TIME:IN T_CLOCK_TIME;
LOAD_NEW_C,CLK,RESET:IN STD_LOGIC;
CURRENT_TIME:OUT T_CLOCK_TIME);
END ENTITY COUNTER;
ARCHITECTURE ART OF COUNTER IS
SIGNAL I_CURRENT_TIME:T_CLOCK_TIME;
BEGIN
PROCESS(CLK,RESET,LOAD_NEW_C) IS
VARIABLE C_T:T_CLOCK_TIME;
BEGIN
IF RISING_EDGE(CLK) THEN
IF RESET='1' THEN
I_CURRENT_TIME(5)<=0;
I_CURRENT_TIME(4)<=0;
I_CURRENT_TIME(3)<=0;
I_CURRENT_TIME(2)<=0;
I_CURRENT_TIME(1)<=0;
I_CURRENT_TIME(0)<=0;
ELSIF LOAD_NEW_C='1' THEN
I_CURRENT_TIME<=NEW_CURRENT_TIME;
ELSE
C_T:=I_CURRENT_TIME;
IF C_T(0)<9 THEN
C_T(0):=C_T(0)+1;
ELSE
C_T(0):=0;
IF C_T(1)<5 THEN
C_T(1):=C_T(1)+1;
ELSE
C_T(1):=0;
IF C_T(2)<9 THEN
C_T(2):=C_T(2)+1;
ELSE
C_T(2):=0;
IF C_T(3)<5 THEN
C_T(3):=C_T(3)+1;
ELSE
C_T(3):=0;
IF C_T(5)<2 THEN
IF C_T(4)<9 THEN
C_T(4):=C_T(4)+1;
ELSE
C_T(4):=0;
C_T(5):=C_T(5)+1;
END IF;
ELSE
IF C_T(4)<3 THEN
C_T(4):=C_T(4)+1;
ELSE
C_T(4):=0;
C_T(5):=0;
END IF;
END IF;
END IF;
END IF;
END IF;
-- I_CURRENT_TIME<=C_T;
END IF;
I_CURRENT_TIME<=C_T;
END IF;
--END IF;
END IF;
END PROCESS;
CURRENT_TIME<=I_CURRENT_TIME;
END ARCHITECTURE ART;
--------------------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY DIVIDER IS
PORT(CLK_IN:STD_LOGIC;
RESET:IN STD_LOGIC;
CLK_OUT:OUT STD_LOGIC);
END ENTITY DIVIDER;
ARCHITECTURE ART OF DIVIDER IS
CONSTANT DIVIDE_PERIOD:T_SHORT:=5;--6000
BEGIN
PROCESS(CLK_IN,RESET) IS
VARIABLE CNT:T_SHORT;
BEGIN
IF (RESET='1') THEN
CNT:=0;
CLK_OUT<='0';
ELSIF RISING_EDGE(CLK_IN) THEN
IF (CNT<=(DIVIDE_PERIOD/2)) THEN
CLK_OUT<='1';
CNT:=CNT+1;
ELSIF (CNT<(DIVIDE_PERIOD-1)) THEN
CLK_OUT<='0';
CNT:=CNT+1;
ELSE
CNT:=0;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART;
-------------------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.P_ALARM.ALL;
ENTITY DRIVER IS
PORT(KEYNUM:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK:IN STD_LOGIC;
ALARM_TIME:IN T_CLOCK_TIME;
CURRENT_TIME:IN T_CLOCK_TIME;
NEW_TIME:IN T_CLOCK_TIME;
SHOW_NEW_TIME:IN STD_LOGIC;
SHOW_A:IN STD_LOGIC;
SOUND_ALARM:OUT STD_LOGIC;
LEDW:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
SEG7:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY DRIVER;
ARCHITECTURE ART OF DRIVER IS
SIGNAL DISPLAY_TIME:T_CLOCK_TIME;
SIGNAL TEMP:INTEGER RANGE 0 TO 9;
SIGNAL CNT:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(ALARM_TIME,CURRENT_TIME,SHOW_A,SHOW_NEW_TIME) IS
BEGIN
--SOUND_LP:FOR I IN ALARM_TIME'RANGE LOOP
IF ((ALARM_TIME(0)=CURRENT_TIME(0)) AND (ALARM_TIME(1)=CURRENT_TIME(1))
AND(ALARM_TIME(2)=CURRENT_TIME(2))AND(ALARM_TIME(3)=CURRENT_TIME(3))AND(ALARM_TIME(4)=CURRENT_TIME(4))
AND (ALARM_TIME(5)=CURRENT_TIME(5)))THEN --IF NOT(ALARM_TIME(I)=CURRENT_TIME(I))THEN
SOUND_ALARM<='1';
--EXIT SOUND_LP;
ELSE
SOUND_ALARM<='0';
END IF;
--END LOOP SOUND_LP;
IF SHOW_NEW_TIME='1' THEN
DISPLAY_TIME<=NEW_TIME;
ELSIF SHOW_A='1' THEN
DISPLAY_TIME<=ALARM_TIME;
ELSIF SHOW_A='0' THEN
DISPLAY_TIME<=CURRENT_TIME;
END IF;
END PROCESS;
PROCESS(CLK) IS
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CNT="111" THEN
CNT<="000";
ELSE
CNT<=CNT+'1';
END IF;
END IF;
END PROCESS;
LEDW<=CNT;
PROCESS(CNT)
BEGIN
CASE CNT IS
WHEN "000" => TEMP<=DISPLAY_TIME(0);
WHEN "001" => TEMP<=DISPLAY_TIME(1);
WHEN "010" => TEMP<=DISPLAY_TIME(2);
WHEN "011" => TEMP<=DISPLAY_TIME(3);
WHEN "100" => TEMP<=DISPLAY_TIME(4);
WHEN "101" => TEMP<=DISPLAY_TIME(5);
WHEN "111" => TEMP<=CONV_INTEGER(KEYNUM);
WHEN OTHERS=>TEMP<=0;
END CASE;
CASE TEMP IS
WHEN 0=> SEG7<="00111111";
WHEN 1=> SEG7<="00000110";
WHEN 2=> SEG7<="01011011";
WHEN 3=> SEG7<="01001111";
WHEN 4=> SEG7<="01100110";
WHEN 5=> SEG7<="01101101";
WHEN 6=> SEG7<="01111101";
WHEN 7=> SEG7<="00000111";
WHEN 8=> SEG7<="01111111";
WHEN 9=> SEG7<="01101111";
WHEN OTHERS=> SEG7<="00111111";
END CASE;
END PROCESS;
END ARCHITECTURE ART;
--------------------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.P_ALARM.ALL;
ENTITY REG IS
PORT(NEW_ALARM_TIME:IN T_CLOCK_TIME;
LOAD_NEW_A:IN STD_LOGIC;
CLK:IN STD_LOGIC;
RESET:IN STD_LOGIC;
ALARM_TIME:OUT T_CLOCK_TIME);
END ENTITY REG;
ARCHITECTURE ART OF REG IS
BEGIN
PROCESS(CLK,RESET) IS
BEGIN
IF RESET='1' THEN
ALARM_TIME(0)<=0;
ALARM_TIME(1)<=0;
ALARM_TIME(2)<=0;
ALARM_TIME(3)<=0;
ALARM_TIME(4)<=0;
ALARM_TIME(5)<=0;
ELSE
IF RISING_EDGE(CLK) THEN
IF LOAD_NEW_A='1' THEN
ALARM_TIME<=NEW_ALARM_TIME;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART;
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