clkdiv.vhd

来自「source code of counter,ram,lfsr etc」· VHDL 代码 · 共 36 行

entity Ad_Clk_Div is
 port(
 Div_Fac : in unsigned(3 downto 0);-- Division Factor
 Clk : in std_logic; -- Global Clk
 Reset : in std_logic; -- Global Reset



 DClk : out std_logic -- Divided Clk Out

 );
 end entity Ad_Clk_Div;

 architecture Ad_Clk_Div_Arch of Ad_Clk_Div is

 signal count : unsigned(3 downto 0);
 begin

 -- Sequential Process
 -- Programmable Load counter and Toggle FiFo
 process(Clk,Reset)
 begin
 if(Reset = '0')then
count <= (others => '0');
 DClk <= '0';
 elsif(RISING_EDGE(Clk))then
 if(count = Div_Fac)then
 count <= (others => '0');
 DClk <= not DClk ;
 else
 count <= count + 1 ;
 end if;
 end if;

 end process;
 end architecture Ad_Clk_Div_Arch;