lfsr.vhd

来自「source code of counter,ram,lfsr etc」· VHDL 代码 · 共 20 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity lfsr_10 is
generic (initval:std_logic_vector (9 downto 0) := "0000000001");
port ( clk: in std_logic;
randout: buffer std_logic_vector(9 downto 0) := initval);
end lfsr_10;

architecture dataflow of lfsr_10 is
signal din: std_logic_vector (9 downto 0);
begin 
 process(clk) begin
if(clk'event AND clk='1') then
din <= randout;
end if; 
din(0) <= randout(9) XOR randout(0);
randout<= din(8 downto 0)& din(0);
end process;

end dataflow;