count.vhd

来自「source code of counter,ram,lfsr etc」· VHDL 代码 · 共 56 行

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is

      port( clkIN : in std_logic;

                  

                  count : out std_logic_vector(9 downto 0));

end counter;
architecture Behavioral of counter is



begin

      process(clkIN)

            variable ccount : integer range 0 to 1024; 
            variable count1 : integer range 0 to 1024;             

      begin
            if clkIN'event and clkIN = '1' then

                  ccount := ccount +1;

                  

            if ccount = 1024 then

                  ccount := 0;            

            end if;

--          ccount2 <= ccount;

 

            count1 := ccount;

            end if;

            
             count <= conv_std_logic_vector(count1, 10);            

      end process;

 

end Behavioral;