led2.tan.rpt

采用Verilog hdl编程语言实现led显示

; N/A   ; None         ; 8.696 ns   ; CS1~reg0 ; CS1 ; CLK        ;
; N/A   ; None         ; 8.634 ns   ; a~reg0   ; a   ; CLK        ;
+-------+--------------+------------+----------+-----+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -1.800 ns ; D3   ; b~reg0 ; CLK      ;
; N/A           ; None        ; -1.800 ns ; D3   ; g~reg0 ; CLK      ;
; N/A           ; None        ; -1.804 ns ; D3   ; c~reg0 ; CLK      ;
; N/A           ; None        ; -1.828 ns ; D0   ; b~reg0 ; CLK      ;
; N/A           ; None        ; -1.835 ns ; D0   ; g~reg0 ; CLK      ;
; N/A           ; None        ; -1.840 ns ; D0   ; c~reg0 ; CLK      ;
; N/A           ; None        ; -1.861 ns ; D3   ; a~reg0 ; CLK      ;
; N/A           ; None        ; -1.937 ns ; D0   ; a~reg0 ; CLK      ;
; N/A           ; None        ; -1.958 ns ; D2   ; f~reg0 ; CLK      ;
; N/A           ; None        ; -1.977 ns ; D2   ; c~reg0 ; CLK      ;
; N/A           ; None        ; -1.984 ns ; D2   ; g~reg0 ; CLK      ;
; N/A           ; None        ; -1.986 ns ; D2   ; b~reg0 ; CLK      ;
; N/A           ; None        ; -1.996 ns ; D1   ; a~reg0 ; CLK      ;
; N/A           ; None        ; -2.012 ns ; D1   ; b~reg0 ; CLK      ;
; N/A           ; None        ; -2.020 ns ; D1   ; g~reg0 ; CLK      ;
; N/A           ; None        ; -2.025 ns ; D1   ; c~reg0 ; CLK      ;
; N/A           ; None        ; -2.033 ns ; D2   ; a~reg0 ; CLK      ;
; N/A           ; None        ; -2.083 ns ; D3   ; d~reg0 ; CLK      ;
; N/A           ; None        ; -2.162 ns ; D0   ; d~reg0 ; CLK      ;
; N/A           ; None        ; -2.229 ns ; D1   ; d~reg0 ; CLK      ;
; N/A           ; None        ; -2.246 ns ; D0   ; e~reg0 ; CLK      ;
; N/A           ; None        ; -2.254 ns ; D2   ; d~reg0 ; CLK      ;
; N/A           ; None        ; -2.312 ns ; D3   ; e~reg0 ; CLK      ;
; N/A           ; None        ; -2.327 ns ; D3   ; f~reg0 ; CLK      ;
; N/A           ; None        ; -2.349 ns ; D1   ; f~reg0 ; CLK      ;
; N/A           ; None        ; -2.399 ns ; D2   ; e~reg0 ; CLK      ;
; N/A           ; None        ; -2.466 ns ; D0   ; f~reg0 ; CLK      ;
; N/A           ; None        ; -2.477 ns ; D1   ; e~reg0 ; CLK      ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Mar 01 19:04:50 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LED2 -c LED2
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 95.54 MHz between source register "buffer[2]" and destination register "b~reg0" (period= 10.467 ns)
    Info: + Longest register to register delay is 9.758 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N4; Fanout = 3; REG Node = 'buffer[2]'
        Info: 2: + IC(1.276 ns) + CELL(0.747 ns) = 2.023 ns; Loc. = LC_X4_Y2_N2; Fanout = 2; COMB Node = 'Add0~122'
        Info: 3: + IC(0.000 ns) + CELL(0.815 ns) = 2.838 ns; Loc. = LC_X4_Y2_N3; Fanout = 2; COMB Node = 'Add0~123'
        Info: 4: + IC(2.442 ns) + CELL(0.740 ns) = 6.020 ns; Loc. = LC_X3_Y1_N0; Fanout = 1; COMB Node = 'Equal0~88'
        Info: 5: + IC(0.756 ns) + CELL(0.511 ns) = 7.287 ns; Loc. = LC_X3_Y1_N1; Fanout = 16; COMB Node = 'Equal0~89'
        Info: 6: + IC(1.228 ns) + CELL(1.243 ns) = 9.758 ns; Loc. = LC_X4_Y1_N1; Fanout = 1; REG Node = 'b~reg0'
        Info: Total cell delay = 4.056 ns ( 41.57 % )
        Info: Total interconnect delay = 5.702 ns ( 58.43 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y1_N1; Fanout = 1; REG Node = 'b~reg0'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y2_N4; Fanout = 3; REG Node = 'buffer[2]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "f~reg0" (data pin = "D2", clock pin = "CLK") is 3.456 ns
    Info: + Longest pin to register delay is 6.471 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_40; Fanout = 8; PIN Node = 'D2'
        Info: 2: + IC(2.835 ns) + CELL(0.740 ns) = 4.707 ns; Loc. = LC_X3_Y1_N6; Fanout = 4; COMB Node = 'a~262'
        Info: 3: + IC(1.173 ns) + CELL(0.591 ns) = 6.471 ns; Loc. = LC_X3_Y1_N3; Fanout = 1; REG Node = 'f~reg0'
        Info: Total cell delay = 2.463 ns ( 38.06 % )
        Info: Total interconnect delay = 4.008 ns ( 61.94 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y1_N3; Fanout = 1; REG Node = 'f~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
Info: tco from clock "CLK" to destination pin "g" through register "g~reg0" is 8.823 ns
    Info: + Longest clock path from clock "CLK" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y1_N4; Fanout = 1; REG Node = 'g~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 5.099 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y1_N4; Fanout = 1; REG Node = 'g~reg0'
        Info: 2: + IC(2.777 ns) + CELL(2.322 ns) = 5.099 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'g'
        Info: Total cell delay = 2.322 ns ( 45.54 % )
        Info: Total interconnect delay = 2.777 ns ( 54.46 % )
Info: th for register "b~reg0" (data pin = "D3", clock pin = "CLK") is -1.800 ns
    Info: + Longest clock path from clock "CLK" to destination register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y1_N1; Fanout = 1; REG Node = 'b~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.369 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 8; PIN Node = 'D3'
        Info: 2: + IC(2.830 ns) + CELL(0.511 ns) = 4.473 ns; Loc. = LC_X4_Y1_N0; Fanout = 1; COMB Node = 'WideOr1~30'
        Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 5.369 ns; Loc. = LC_X4_Y1_N1; Fanout = 1; REG Node = 'b~reg0'
        Info: Total cell delay = 2.234 ns ( 41.61 % )
        Info: Total interconnect delay = 3.135 ns ( 58.39 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Sun Mar 01 19:04:51 2009
    Info: Elapsed time: 00:00:01