led2.fit.smsg

采用Verilog hdl编程语言实现led显示

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Mar 01 19:06:14 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LED2 -c LED2
Info: Selected device EPM240T100C5 for design "LED2"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 9.219 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y3; Fanout = 2; REG Node = 'buffer[4]'
    Info: 2: + IC(2.041 ns) + CELL(1.244 ns) = 3.285 ns; Loc. = LAB_X4_Y2; Fanout = 3; COMB Node = 'Add0~126'
    Info: 3: + IC(0.000 ns) + CELL(1.234 ns) = 4.519 ns; Loc. = LAB_X4_Y2; Fanout = 2; COMB Node = 'Add0~129'
    Info: 4: + IC(2.074 ns) + CELL(0.200 ns) = 6.793 ns; Loc. = LAB_X3_Y1; Fanout = 16; COMB Node = 'Equal0~89'
    Info: 5: + IC(1.183 ns) + CELL(1.243 ns) = 9.219 ns; Loc. = LAB_X4_Y1; Fanout = 1; REG Node = 'b~reg0'
    Info: Total cell delay = 3.921 ns ( 42.53 % )
    Info: Total interconnect delay = 5.298 ns ( 57.47 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 3%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 154 megabytes of memory during processing
    Info: Processing ended: Sun Mar 01 19:06:19 2009
    Info: Elapsed time: 00:00:05