led2.map.rpt

采用Verilog hdl编程语言实现led显示

+----------------------------------+-----------------+-----------+-------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path        ;
+----------------------------------+-----------------+-----------+-------------------------------------+
; LED2.v                           ; yes             ; Other     ; E:/张永顺/FPGA/助学活动/LED2/LED2.v ;
+----------------------------------+-----------------+-----------+-------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 34    ;
;     -- Combinational with no register       ; 18    ;
;     -- Register only                        ; 8     ;
;     -- Combinational with a register        ; 8     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 13    ;
;     -- 3 input functions                    ; 4     ;
;     -- 2 input functions                    ; 8     ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 27    ;
;     -- arithmetic mode                      ; 7     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 16    ;
; Total logic cells in carry chains           ; 8     ;
; I/O pins                                    ; 14    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 16    ;
; Total fan-out                               ; 114   ;
; Average fan-out                             ; 2.38  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |LED2                      ; 34 (34)     ; 16           ; 0          ; 14   ; 0            ; 18 (18)      ; 8 (8)             ; 8 (8)            ; 8 (8)           ; 0 (0)      ; |LED2               ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------+
; Registers Removed During Synthesis                           ;
+---------------------------------------+----------------------+
; Register name                         ; Reason for Removal   ;
+---------------------------------------+----------------------+
; CS2~reg0                              ; Merged with CS1~reg0 ;
; Total Number of Removed Registers = 1 ;                      ;
+---------------------------------------+----------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 16    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |LED2|b~reg0               ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |LED2|a~reg0               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sun Mar 01 19:06:10 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LED2 -c LED2
Warning: Using design file LED2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: LED2
Info: Elaborating entity "LED2" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at LED2.v(13): truncated value with size 32 to match size of target (8)
Info: Duplicate registers merged to single register
    Info: Duplicate register "CS2~reg0" merged to single register "CS1~reg0", power-up level changed
Info: Implemented 48 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 9 output pins
    Info: Implemented 34 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 123 megabytes of memory during processing
    Info: Processing ended: Sun Mar 01 19:06:12 2009
    Info: Elapsed time: 00:00:02