led2.map.eqn

采用Verilog hdl编程语言实现led显示

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L26Q is a~reg0
--operation mode is normal

A1L26Q_lut_out = A1L56 & (A1L24 & (!A1L49) # !A1L24 & A1L25) # !A1L56 & (!A1L49);
A1L26Q = DFFEAS(A1L26Q_lut_out, CLK, VCC, , A1L56, , , , );


--A1L37Q is b~reg0
--operation mode is normal

A1L37Q_lut_out = A1L50 # A1L56 & (!A1L24);
A1L37Q = DFFEAS(A1L37Q_lut_out, CLK, VCC, , A1L56, , , , );


--A1L40Q is c~reg0
--operation mode is normal

A1L40Q_lut_out = A1L56 & !A1L24 # !A1L39;
A1L40Q = DFFEAS(A1L40Q_lut_out, CLK, VCC, , A1L56, , , , );


--A1L42Q is d~reg0
--operation mode is normal

A1L42Q_lut_out = A1L56 & (A1L24 & (!A1L51) # !A1L24 & A1L25) # !A1L56 & (!A1L51);
A1L42Q = DFFEAS(A1L42Q_lut_out, CLK, VCC, , A1L56, , , , );


--A1L44Q is e~reg0
--operation mode is normal

A1L44Q_lut_out = A1L56 & (A1L24 & A1L52 # !A1L24 & (A1L25)) # !A1L56 & A1L52;
A1L44Q = DFFEAS(A1L44Q_lut_out, CLK, VCC, , A1L56, , , , );


--A1L46Q is f~reg0
--operation mode is normal

A1L46Q_lut_out = A1L56 & (A1L24 & (!A1L53) # !A1L24 & A1L25) # !A1L56 & (!A1L53);
A1L46Q = DFFEAS(A1L46Q_lut_out, CLK, VCC, , A1L56, , , , );


--A1L48Q is g~reg0
--operation mode is normal

A1L48Q_lut_out = !A1L54 & (A1L24 # !A1L56);
A1L48Q = DFFEAS(A1L48Q_lut_out, CLK, VCC, , A1L56, , , , );


--A1L3Q is CS1~reg0
--operation mode is normal

A1L3Q_lut_out = A1L56 & (!A1L24);
A1L3Q = DFFEAS(A1L3Q_lut_out, CLK, VCC, , A1L56, , , , );


--A1L25 is a~142
--operation mode is normal

A1L25 = D3 # D2 & D1;


--A1L10 is add~121
--operation mode is arithmetic

A1L10 = !buffer[0];

--A1L11 is add~123
--operation mode is arithmetic

A1L11 = CARRY(buffer[0]);


--A1L12 is add~126
--operation mode is arithmetic

A1L12_carry_eqn = A1L11;
A1L12 = buffer[1] $ (A1L12_carry_eqn);

--A1L13 is add~128
--operation mode is arithmetic

A1L13 = CARRY(!A1L11 # !buffer[1]);


--A1L14 is add~131
--operation mode is arithmetic

A1L14_carry_eqn = A1L13;
A1L14 = buffer[2] $ (!A1L14_carry_eqn);

--A1L15 is add~133
--operation mode is arithmetic

A1L15 = CARRY(buffer[2] & (!A1L13));


--A1L16 is add~136
--operation mode is arithmetic

A1L16_carry_eqn = A1L15;
A1L16 = buffer[3] $ (A1L16_carry_eqn);

--A1L17 is add~138
--operation mode is arithmetic

A1L17 = CARRY(!A1L15 # !buffer[3]);


--A1L55 is rtl~93
--operation mode is normal

A1L55 = !A1L10 & !A1L12 & !A1L14 & !A1L16;


--A1L18 is add~141
--operation mode is arithmetic

A1L18_carry_eqn = A1L17;
A1L18 = buffer[4] $ (!A1L18_carry_eqn);

--A1L19 is add~143
--operation mode is arithmetic

A1L19 = CARRY(buffer[4] & (!A1L17));


--A1L20 is add~146
--operation mode is arithmetic

A1L20_carry_eqn = A1L19;
A1L20 = buffer[5] $ (A1L20_carry_eqn);

--A1L21 is add~148
--operation mode is arithmetic

A1L21 = CARRY(!A1L19 # !buffer[5]);


--A1L22 is add~151
--operation mode is arithmetic

A1L22_carry_eqn = A1L21;
A1L22 = buffer[6] $ (!A1L22_carry_eqn);

--A1L23 is add~153
--operation mode is arithmetic

A1L23 = CARRY(buffer[6] & (!A1L21));


--A1L56 is rtl~94
--operation mode is normal

A1L56 = A1L55 & !A1L18 & !A1L20 & !A1L22;


--A1L24 is add~156
--operation mode is normal

A1L24_carry_eqn = A1L23;
A1L24 = buffer[7] $ (A1L24_carry_eqn);


--A1L49 is reduce_or~106
--operation mode is normal

A1L49 = D0 & !D2 & (D1 $ !D3) # !D0 & D2 & (D1 $ !D3);


--A1L50 is reduce_or~107
--operation mode is normal

A1L50 = D2 # D0 & (D1 # !D3) # !D0 & (D1 $ D3);


--A1L39 is c~39
--operation mode is normal

A1L39 = D0 & (D1 & !D2 & !D3 # !D1 & D2 & D3);


--A1L51 is reduce_or~108
--operation mode is normal

A1L51 = D0 & !D2 & (D1 $ !D3) # !D0 & (D1 & D2 & D3 # !D1 & (D2 $ D3));


--A1L52 is reduce_or~109
--operation mode is normal

A1L52 = D0 & (D2 # D1 $ D3);


--A1L53 is reduce_or~110
--operation mode is normal

A1L53 = D1 & (D2 & !D0 & D3 # !D2 & (!D3)) # !D1 & (D0 & D2 & D3 # !D0 & (D2 # D3));


--A1L54 is reduce_or~111
--operation mode is normal

A1L54 = D2 & (D1 $ !D3) # !D2 & !D0 & !D1 & D3;


--buffer[0] is buffer[0]
--operation mode is normal

buffer[0]_lut_out = A1L10;
buffer[0] = DFFEAS(buffer[0]_lut_out, CLK, VCC, , , , , , );


--buffer[1] is buffer[1]
--operation mode is normal

buffer[1]_lut_out = A1L12;
buffer[1] = DFFEAS(buffer[1]_lut_out, CLK, VCC, , , , , , );


--buffer[2] is buffer[2]
--operation mode is normal

buffer[2]_lut_out = A1L14;
buffer[2] = DFFEAS(buffer[2]_lut_out, CLK, VCC, , , , , , );


--buffer[3] is buffer[3]
--operation mode is normal

buffer[3]_lut_out = A1L16;
buffer[3] = DFFEAS(buffer[3]_lut_out, CLK, VCC, , , , , , );


--buffer[4] is buffer[4]
--operation mode is normal

buffer[4]_lut_out = A1L18;
buffer[4] = DFFEAS(buffer[4]_lut_out, CLK, VCC, , , , , , );


--buffer[5] is buffer[5]
--operation mode is normal

buffer[5]_lut_out = A1L20;
buffer[5] = DFFEAS(buffer[5]_lut_out, CLK, VCC, , , , , , );


--buffer[6] is buffer[6]
--operation mode is normal

buffer[6]_lut_out = A1L22;
buffer[6] = DFFEAS(buffer[6]_lut_out, CLK, VCC, , , , , , );


--buffer[7] is buffer[7]
--operation mode is normal

buffer[7]_lut_out = A1L24;
buffer[7] = DFFEAS(buffer[7]_lut_out, CLK, VCC, , , , , , );


--D3 is D3
--operation mode is input

D3 = INPUT();


--D2 is D2
--operation mode is input

D2 = INPUT();


--D1 is D1
--operation mode is input

D1 = INPUT();


--D0 is D0
--operation mode is input

D0 = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--a is a
--operation mode is output

a = OUTPUT(A1L26Q);


--b is b
--operation mode is output

b = OUTPUT(A1L37Q);


--c is c
--operation mode is output

c = OUTPUT(A1L40Q);


--d is d
--operation mode is output

d = OUTPUT(A1L42Q);


--e is e
--operation mode is output

e = OUTPUT(A1L44Q);


--f is f
--operation mode is output

f = OUTPUT(A1L46Q);


--g is g
--operation mode is output

g = OUTPUT(A1L48Q);


--CS1 is CS1
--operation mode is output

CS1 = OUTPUT(A1L3Q);


--CS2 is CS2
--operation mode is output

CS2 = OUTPUT(!A1L3Q);