count10.vhdl

利用fpga实现秒表。秒表有开始停止

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count10 is
port(clk:in std_logic;
     reset:in std_logic;
	enable:in std_logic;
	data:out std_logic_vector(3 downto 0);
	carry:out std_logic);
end count10;

architecture Behavioral of count10 is
   signal q:integer range 0 to 9:=0;

begin
process(enable,clk,reset)
begin
  if enable='0' then
  if  reset='0' then q<=0;
  else if clk'event and clk='1' then
          if q=9 then  q<=0;	
	     else q<=q+1; 
	     end if;
	  end if;

  end if;
  end if;
  end process;
data <="0000"when q=0 else
        "0001"when q=1 else
        "0010"when q=2 else
        "0011"when q=3 else
        "0100"when q=4 else
        "0101"when q=5 else
        "0110"when q=6 else
	   "0111"when q=7 else
	   "1000"when q=8 else
	   "1001"when q=9 else
	   "1111";
carry<='1' when reset ='0' else
        '0' when q=9 and enable='0'else
	   '1' ;

end Behavioral;