fenpin.vhdl

来自「利用fpga实现秒表。秒表有开始停止」· VHDL 代码 · 共 35 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fenpin is
  port(clk1:in std_logic;
       clk100:out std_logic);
	    

end fenpin;

architecture Behavioral of fenpin is
 signal q:integer range 0 to 160000:=0;
 signal clk2 :std_logic:='0';

begin
process(clk1)
begin 
if clk1'event and clk1='1' then
    if q=159999 then 
    q<=0; clk2<= not clk2;
    else
    q<=q+1;
    end if;
 end if;
 end process;

 clk100<=clk2;
end Behavioral;