display.vhdl

来自「利用fpga实现秒表。秒表有开始停止」· VHDL 代码 · 共 34 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity display is
port(datain: in std_logic_vector(3 downto 0);
    dataout: out std_logic_vector(6 downto 0));
end display;

architecture Behavioral of display is
begin
process(datain)
  begin
      case datain is 
    when "0000"=>  dataout<="0000001";
    when "0001"=>  dataout<="1001111";           
    when "0010"=>  dataout<="0010010";
    when "0011"=>  dataout<="0000110";
    when "0100"=>  dataout<="1001100";
    when "0101"=>  dataout<="0100100";
    when "0110"=>  dataout<="0100000";
    when "0111"=>  dataout<="0001111";
    when "1000"=>  dataout<="0000000";
    when "1001"=>  dataout<="0000100";
    when others => dataout<="0000001";
	end case;
end process;
end Behavioral;