simple_calc_tb.vhd

来自「关于xilinx环境下的电路设计」· VHDL 代码 · 共 33 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY SIMPLE_CALC_TB_vhd IS
END SIMPLE_CALC_TB_vhd;

ARCHITECTURE TEST OF SIMPLE_CALC_TB_vhd IS 
	COMPONENT simple_calc
	PORT(	CLK_IN : IN std_logic;          
		   RESET : in std_logic;
			RESULT_OUT : OUT std_logic
		);
	END COMPONENT;

	SIGNAL CLK_TB 		:  std_logic := '0';
  	SIGNAL RESET_TB :  std_logic := '0';
	SIGNAL RESULT 	:  std_logic;

BEGIN
 
	uut: simple_calc PORT MAP(
		CLK_IN => CLK_TB,
		RESET => RESET_TB,
		RESULT_OUT => RESULT
	);

  CLK_TB <= not CLK_TB after 10 ns;
  RESET_TB <= '1' after 5 ns, '0' after 10 ns, '1' after 700 ns, '0' after 725 ns;  

END architecture TEST;