mem.vhd

来自「关于xilinx环境下的电路设计」· VHDL 代码 · 共 49 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.CALC1_PAK.ALL;

entity MEM is
    Port ( CLK, EN: in std_logic ;
	        ADDR : in std_logic_vector(2 downto 0):="000";  -- initialize for simulation 
	        DATA_FRAME : out MY_RECORD );
end entity MEM;

architecture RTL of MEM is

type ROM_ARRAY is array ( 0 to 5 ) of MY_RECORD;

constant MY_ROM : ROM_ARRAY := 
  ( 0 => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ),
    1 => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ),
    2 => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ),
    3 => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ),
    4 => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ),
    5 => ( A_IN => "0000", B_IN => "0000", OP_CODE => "0000", C_IN => '0', EXP_OUT => "0000" ));
--
-- ROM with actual contents, to be used later
--
--constant MY_ROM : ROM_ARRAY := 
--  ( 0 => ( A_IN => "1000", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "1010" ),
--    1 => ( A_IN => "0100", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "0110" ),
--    2 => ( A_IN => "0010", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "0100" ),
--    3 => ( A_IN => "0001", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "0011" ), -- induce error
--    4 => ( A_IN => "0011", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "0101" ),
--    5 => ( A_IN => "0111", B_IN => "0010", OP_CODE => "0001", C_IN => '0', EXP_OUT => "1001" ));
--
--

begin									 	 
	    
process ( CLK )
    begin
	    if rising_edge ( CLK) then 
		   if ( EN = '1') then	     
		  DATA_FRAME <= MY_ROM(conv_integer(ADDR)) ; 
		 end if;
		end if;
end process ;	  
	  	
end RTL;