simple_calc.vhd

关于xilinx环境下的电路设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.CALC1_PAK.all;

entity SIMPLE_CALC is
    generic ( SYNTH : boolean := false );
	 port    ( CLK_IN : in std_logic;
				  RESET: in std_logic;				   
              RESULT_OUT : out std_logic);
end SIMPLE_CALC;

architecture STRUCTURAL of SIMPLE_CALC is

COMPONENT CNTRL_FSM 
    Port ( DATA_FRAME : in MY_RECORD;
           CLK : in std_logic;
			  RESET : in std_logic ;
			  A_IN : out std_logic_vector(3 downto 0);
           B_IN : out std_logic_vector(3 downto 0);
           C_IN : out std_logic;
           OP_CODE : out std_logic_vector(3 downto 0);
           EXP : out std_logic_vector(3 downto 0);
           ADDR : out std_logic_vector ( 2 downto 0);
			  COMP_EN : out std_logic;
			  ALU_EN : out std_logic;
			  MEM_EN : out std_logic  
			   );
end component;

COMPONENT ALU
	PORT(	 
		CLK : IN std_logic ;
		OP_CODE : IN std_logic_vector(3 downto 0);
		A : IN std_logic_vector(3 downto 0);
		B : IN std_logic_vector(3 downto 0);
		C_IN : IN std_logic;          
		Y : OUT std_logic_vector(3 downto 0);
		EN : in std_logic
		);
	END COMPONENT;	

COMPONENT MEM 
    Port ( CLK : std_logic ;
	        EN : std_logic ;
	        ADDR : in std_logic_vector(2 downto 0);
	        DATA_FRAME : out MY_RECORD );
end component;

COMPONENT COMP
	PORT(
		CLK : in std_logic ;
		EXPECTED : IN std_logic_vector(3 downto 0);
		ALU_OUT : IN std_logic_vector(3 downto 0);          
		RESULT : OUT std_logic;
		EN : in std_logic
		);
	END COMPONENT;

COMPONENT COMP_RTL
	PORT(
		CLK : in std_logic ;
		EXPECTED : IN std_logic_vector(3 downto 0);
		ALU_OUT : IN std_logic_vector(3 downto 0);          
		RESULT : OUT std_logic;
		EN : in std_logic
		);
	END COMPONENT;
	
  signal EXP_OUT_SIG : std_logic_vector ( 3 downto 0);
  signal A_IN_SIG : std_logic_vector ( 3 downto 0);
  signal B_IN_SIG :std_logic_vector ( 3 downto 0);
  signal OP_CODE_SIG :std_logic_vector ( 3 downto 0);
  signal CI_SIG : std_logic;
  signal ALU_EN_SIG : std_logic;
  signal COMP_EN_SIG : std_logic;
  signal MEM_EN_SIG : std_logic;
  signal ALU_OUT_SIG :std_logic_vector ( 3 downto 0);
  signal ADDR_SIG :std_logic_vector ( 2 downto 0);
  signal DATA_FRAME_SIG :MY_RECORD ;

begin
  	MEM_INST0: MEM PORT MAP(
		ADDR => ADDR_SIG,
		DATA_FRAME => DATA_FRAME_SIG,
		EN => MEM_EN_SIG,
      CLK => CLK_IN ) ;	 
		 
	  
	ALU_INST0: ALU PORT MAP(
		OP_CODE => OP_CODE_SIG,
		A => A_IN_SIG,
		B => B_IN_SIG,
		C_IN => CI_SIG,
		Y => ALU_OUT_SIG,
		EN => ALU_EN_SIG,
		 CLK => CLK_IN
		 	);

	CNTRL_FSM_INST0: CNTRL_FSM  PORT MAP(
		ADDR => ADDR_SIG,
		DATA_FRAME => DATA_FRAME_SIG,
		OP_CODE => OP_CODE_SIG,
		A_IN => A_IN_SIG,
		B_IN => B_IN_SIG,
		C_IN => CI_SIG,
		EXP => EXP_OUT_SIG,
		CLK => CLK_IN,
		RESET => RESET,
		ALU_EN => ALU_EN_SIG,
		COMP_EN => COMP_EN_SIG,
		MEM_EN => MEM_EN_SIG 	);
								

GEN_SIM : if SYNTH = false generate 
 COMP_INST: component COMP port map (  CLK => CLK_IN, EN => COMP_EN_SIG, EXPECTED => EXP_OUT_SIG, ALU_OUT => ALU_OUT_SIG, RESULT => RESULT_OUT );
end generate GEN_SIM ;
    
GEN_SYNTH : if SYNTH = true generate 
 COMP_INST: component COMP_RTL port map (  CLK => CLK_IN, EN => COMP_EN_SIG, EXPECTED => EXP_OUT_SIG, ALU_OUT => ALU_OUT_SIG, RESULT => RESULT_OUT );
end generate GEN_SYNTH ;

end STRUCTURAL;