comp.vhd

来自「关于xilinx环境下的电路设计」· VHDL 代码 · 共 37 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity COMP is
    Port ( CLK : in std_logic ;
	        EXPECTED : in std_logic_vector(3 downto 0);
           ALU_OUT : in std_logic_vector(3 downto 0);
           EN : in std_logic ;
			  RESULT : out std_logic );
            
end COMP;

architecture Behavioral of COMP is

begin

process  ( CLK )  
  begin
     if rising_edge ( CLK) then
      if (EN = '1') then
       if ( EXPECTED = ALU_OUT )then
		     RESULT <= '1';
		 else 
		     RESULT <= '0' ;
		 end if;
		
		assert (EXPECTED = ALU_OUT )             
		 report " Warning, simulation mismatch has occurred "
		 severity warning ;		 
    				
		end if;
	end if ;			 
	end process; 
end Behavioral;