comp_rtl.vhd

来自「关于xilinx环境下的电路设计」· VHDL 代码 · 共 52 行

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    01:39:14 03/26/05
-- Design Name:    
-- Module Name:    COMP - RTL
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity COMP_RTL is
    Port ( CLK : in std_logic ;
	        EXPECTED : in std_logic_vector(3 downto 0);
	        EN : in std_logic ;
           ALU_OUT : in std_logic_vector(3 downto 0);
           RESULT : out std_logic );
            
end COMP_RTL;

architecture RTL of COMP_RTL is

begin

 process ( CLK )
   begin
    if rising_edge ( CLK ) then  
	  if EN = '1' then 
	   if EXPECTED = ALU_OUT then
	    RESULT <= '1' ;
	    else
	    RESULT <= '0';
	  end if;
	 end if ;
	end if;
  end process;

end RTL;