cntrl_fsm.vhd

关于xilinx环境下的电路设计

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.CALC1_PAK.all;

entity CNTRL_FSM1 is
    port ( DATA_FRAME : in  MY_RECORD;
           CLK        : in  std_logic;
           RESET      : in  std_logic;
           A_IN       : out std_logic_vector(3 downto 0);
           B_IN       : out std_logic_vector(3 downto 0);
           C_IN       : out std_logic;
           OP_CODE    : out std_logic_vector(3 downto 0);
           EXP        : out std_logic_vector(3 downto 0);
           ADDR       : out std_logic_vector ( 2 downto 0);
           COMP_EN    : out std_logic;
           MEM_EN     : out std_logic;
           ALU_EN     : out std_logic );
end entity CNTRL_FSM1;

architecture RTL of CNTRL_FSM1 is

    type CNTRL_STATE is ( S0_INIT, S1_FETCH, S2_ALU, S3_COMP, S4_DONE );
    signal CURR_STATE, NEXT_STATE : CNTRL_STATE;

    signal ADDR_I, ADDR_Q : std_logic_vector ( 2 downto 0 );
begin

    ADDR <= ADDR_Q;                     -- update output port from synchronous internal signal

    SYNC : process ( CLK, RESET )
    begin
        if ( RESET = '1' ) then
            CURR_STATE <= S0_INIT;
            ADDR_Q     <= ( others => '0' );
        elsif rising_edge (CLK) then
            CURR_STATE <= NEXT_STATE;
            ADDR_Q     <= ADDR_I;
        end if;
    end process SYNC;

    COMB : process ( CURR_STATE, DATA_FRAME, ADDR_Q )
    begin
        --default assignments
        A_IN    <= DATA_FRAME.A_IN;
        B_IN    <= DATA_FRAME.B_IN;
        C_IN    <= DATA_FRAME.C_IN;
        OP_CODE <= DATA_FRAME.OP_CODE;
        EXP     <= DATA_FRAME.EXP_OUT;

        ADDR_I <= ADDR_Q;

        case CURR_STATE is

            when S0_INIT =>
                MEM_EN  <= '0';
                ALU_EN  <= '0';
                COMP_EN <= '0';

                NEXT_STATE <= S1_FETCH;

            when S1_FETCH =>
                MEM_EN  <= '1';
                ALU_EN  <= '0';
                COMP_EN <= '0';

                NEXT_STATE <= S2_ALU;


            when S2_ALU =>
                MEM_EN  <= '0';
                ALU_EN  <= '1';
                COMP_EN <= '0';

                NEXT_STATE <= S3_COMP;

            when S3_COMP =>
                MEM_EN  <= '0';
                ALU_EN  <= '0';
                COMP_EN <= '1';

                NEXT_STATE <= S4_DONE;

            when S4_DONE =>
                if ADDR_Q >= "101" then
                    NEXT_STATE <= S4_DONE;
                else
                    NEXT_STATE <= S1_FETCH ;
                    ADDR_I <= ADDR_Q + 1;		         
                end if;	
                MEM_EN <= '0' ;
                ALU_EN <= '0';
                COMP_EN <= '0';
                

            when others =>
                NEXT_STATE <= S0_INIT;
                MEM_EN <= '0' ;
                ALU_EN <= '0';
                COMP_EN <= '0';				    

        end case;

    end process COMB;
    
end RTL;