uat_top.v

it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix

//*****************************************************************************************//
//    Project      : FPGA based Digital Design using Verilog HDL
//    File         : uat_top.v
//    Author       : Irfan Faisal Mir & Nauman Mir
//    Company      : Chip Designing Course
//    Start Date   : 
//    Last Updated : 
//    Version      : 0.1
//    Abstract     : This module implements...........
// 
//    Modification History:
//==========================================================================================
//    Date                       By                    Version            Change Description
//==========================================================================================
//                               Irfan & Nauman        0.1                Original Version
//
//******************************************************************************************//

module uat_top(//Inputs
               clk_x,       //1-bit System Clock input
               rst_n,              //1-bit Asyncronous Active Low Reset input
               din_rdy,            //1-bit ready input signal that indicates the data is ready at input for Tx 
               din_byte,           //8-bit data input in UART for Tx
               // Output
               ser_out             //1-bit Tx data output from UART
              );
// Declaration inputs, outputs 
input       clk_x ;
input       rst_n ;
input       din_rdy ;
input [7:0] din_byte ;  
output      ser_out ;

reg         ser_out;
reg   [7:0] data_buf;         
reg   [2:0] shift_count;
reg         din_rdy_reg;

wire        start_bit_sig;
wire        data_bits_sig;
wire        stop_bit_sig;

// Registered Data Ready Signal
always @(posedge clk_x or negedge rst_n)
begin
  if(~rst_n)
    din_rdy_reg <= #1 1'b0;
  else
    din_rdy_reg <= #1 din_rdy ; 
end 

//Output Logic
//always @(posedge clk_x or posedge rst_n)
always @(negedge clk_x or negedge rst_n)
begin
   if(~rst_n)
      ser_out <= #1 1'b1;
   else 
   begin
     case({start_bit_sig,data_bits_sig,stop_bit_sig})
        3'b100: ser_out <= #1 1'b0;
        3'b010: ser_out <= #1 data_buf[0];
        3'b001: ser_out <= #1 1'b1;
        default: ser_out <= #1 1'b1;
     endcase
   end
end         

// strat bit pipelinin
always @(posedge clk_x or negedge rst_n)
begin
   if(~rst_n)
      data_buf <= #1 8'd0;
   else if(start_bit_sig)
      data_buf <= #1 din_byte;  // at just arriving the start_bit_sig , we load data into data_buffer 
   else if(data_bits_sig)
      data_buf <= #1 {1'b1,data_buf[7:1]};
   else
      data_buf <= #1 data_buf;
end
  
// Counter that count shift in Data Buffer Logic
always @(posedge clk_x or negedge rst_n)
begin
   if(~rst_n)
      shift_count <= #1 3'd0;
   else if(data_bits_sig)
      shift_count <= #1 shift_count + 1; //Counter will start when data is vlaid by High the data_its_sig flag  
   else
      shift_count <= #1 3'd0;
end

// State machine for Tx
uat_sm uat_sm_inst(// Inputs
                   .clk_x               (clk_x        ),
                   .rst_n               (rst_n        ),
                   .din_rdy             (din_rdy_reg  ),   // 1-bit serial data from channel 
                   .shift_count         (shift_count  ),
                   // Outputs         
                   .start_bit_sig       (start_bit_sig),   // Start bit insertion Control Signal generate from State Mechiene
                   .data_bits_sig       (data_bits_sig),   // Data bits insertion Control Signal generate from State Mechiene
                   .stop_bit_sig        (stop_bit_sig )    // Stop Bit insertion  Control Signal generate from State Mechiene
                  );
endmodule