uart_top.v

it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix

//*****************************************************************************************//
//    Project      : FPGA based Digital Design using Verilog HDL
//    File         : uart_top.v
//    Author       : Irfan Faisal Mir & Nauman Mir
//    Company      : Chip Designing Course
//    Start Date   : 
//    Last Updated : 
//    Version      : 0.1
//    Abstract     : This module implements...........
// 
//    Modification History:
//==========================================================================================
//    Date                       By                    Version            Change Description
//==========================================================================================
//                               Irfan & Nauman        0.1                Original Version
//
//******************************************************************************************//

module uart_top(// Inputs
                clk,
                rst_n,
                ser_data_frm_pc,
                // Outputs
                ser_data_to_pc,
                //Monitoring Signals
                clk_x,
                clk_16x
               );
//Inputs
input     clk ;
input     rst_n ;
input     ser_data_frm_pc ;

//output
output    clk_x ;
output    clk_16x ;
output    ser_data_to_pc ;

// Register ,Wire Declaration 
reg [3:0]  count_div ;
reg [7:0]  count_div_153600 ;
reg        clk_16x ;

wire [7:0] dout_byte_wire ;
wire       dout_rdy_wire ;
wire       clk_x ;

/////////////////////////////////////////////////////
//////////////  CLOCK DIVIDER BLOCK /////////////////
/////////////////////////////////////////////////////
always @(posedge clk or negedge rst_n)
begin
  if(~rst_n) begin
    count_div_153600 <= 8'd0 ;
    clk_16x <= 1'b0 ;
  end
  else if(count_div_153600 == 8'd129) begin    // 6'd51
    count_div_153600 <= 8'd0 ;
    clk_16x <= ~clk_16x;
  end  
  else begin
    count_div_153600 <= count_div_153600 + 1;
    clk_16x <= clk_16x;
  end
end

// clk_16x = 153600 Hz
always @(posedge clk_16x or negedge rst_n)
begin
  if(~rst_n)
    count_div <= 4'd0 ;
  else
    count_div <= count_div + 1;
end 

// clk_x = 9600 Hz
assign clk_x = count_div[3];
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////

// Uart Transmitter
uat_top uat_top_inst(//Inputs
                     .clk_x                (clk_x         ),   //1-bit System Clock input
                     .rst_n                (rst_n         ),   //1-bit Asyncronous Active Low Reset input
                     .din_rdy              (dout_rdy_wire ),   //1-bit ready input signal that indicates the data is ready at input for Tx 
                     .din_byte             (dout_byte_wire),   //8-bit data input in UART for Tx
                     // Output             
                     .ser_out              (ser_data_to_pc)   //1-bit Tx data output from UART
                    );

// Uart Reciever
uar_top uar_top_inst(// Inputs
                     .clk_16x              (clk_16x        ),
                     .rst_n                (rst_n          ),
                     .ser_in               (ser_data_frm_pc),
                     // Outputs            
                     .dout_rdy             (dout_rdy_wire  ),
                     .dout_byte            (dout_byte_wire )
                    );
endmodule