minute.vhd

来自「实现嵌入式系统的秒表计时」· VHDL 代码 · 共 43 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity minute is
port
(clk_1HZ : in std_logic; 
 enable:in std_logic;
 m_low:out integer range 0 to 9;
 m_high:out integer range 0 to 5;
count:out std_logic);
end;

architecture minute_arch of minute is
signal ml:integer range 0 to 9;
signal mh:integer range 0 to 5;
signal count_temp:std_logic;
begin
process(clk_1HZ,enable)
begin
if(enable='0')then
null;
else
if(clk_1HZ'event and clk_1HZ='1')then
if(ml=9 and mh=5)then
ml<=0;
mh<=0;
elsif(ml/=9)then
ml<=ml+1;
elsif(ml=9 and mh/=5)then
ml<=0;
mh<=mh+1;
else
ml<=0;mh<=0;
end if;
if(ml=8 and mh=5)then count_temp<='1'; 
        else count_temp<='0';
   		end if;
 end if;
end if;
end process;
m_low<=ml;m_high<=mh;count<=count_temp;
end;