second.vhd

来自「实现嵌入式系统的秒表计时」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity second is
port
(clk_1HZ : in std_logic; 
 enable:in std_logic;
 s_low:out integer range 0 to 9;
 s_high:out integer range 0 to 5;
count:out std_logic);
end;

architecture second_arch of second is
signal sl:integer range 0 to 9;
signal sh:integer range 0 to 5;
signal count_temp:std_logic;
begin
process(clk_1HZ,enable)
begin
if(enable='0')then
null;
else
if(clk_1HZ'event and clk_1HZ='1')then
if(sl=9 and sh=5)then
sl<=0;
sh<=0;
elsif(sl/=9)then
sl<=sl+1;
elsif(sl=9 and sh/=5)then
sl<=0;
sh<=sh+1;
else
sl<=0;sh<=0;
end if;
if(sl=8 and sh=5)then count_temp<='1'; 
        else count_temp<='0';
   		end if;
 end if;
end if;
end process p1;
s_low<=sl;s_high<=sh;count<=count_temp;
end;