u8051int.v

来自「实现USB接口功能的VHDL和verilog完整源代码」· Verilog 代码 · 共 44 行

// This module performs the interfacing of USB controller and 8051 For Monitor

module U8051int (
		suspended,
		usbreset,
		usbclock,
		// 8051 data signal
		endpstatusreg,
		Ucontrolreg,
		mcu0rdready,
		mcu0wrready,
		mcu1wrready,
		enresume,
		intsignal
);

input      usbreset;
input      usbclock;
input      mcu0rdready;  // Endpoint 0 rd fifo enable for USB 
input      mcu0wrready;  // Endpoint 0 wr fifo enable
input      mcu1wrready;  // Endpoint 1 rd fifo enable 
input      suspended;

input[7:0] Ucontrolreg;
output[7:0] endpstatusreg;

output   intsignal;
output   enresume;

wire[7:0]  endpstatusreg = {3'b000,mcu0rdready,mcu0wrready,mcu1wrready,suspended} ;
reg intsignal;
wire  enresume = Ucontrolreg[0];

always@(posedge usbclock)
  begin
	 if(usbreset)
		intsignal = 1'b0;
     else
		intsignal = ( Ucontrolreg[1] &&  mcu0wrready) || (Ucontrolreg[2] && mcu0rdready)
					|| ( Ucontrolreg[0] && mcu1wrready) ;
  end

endmodule