udevconnections.v

来自「实现USB接口功能的VHDL和verilog完整源代码」· Verilog 代码 · 共 36 行

/* 
This file includes all the io signal connections for the
module instantiation that are specific to endpoints
*/

	.currentalternatesetting (currentalternatesetting),

	// connections to endpoint0 - read/write
//	.endp0noncorecmd (endp0noncorecmd),
	.endp0wr (endp0wr),
	.endp0wrready (endp0wrready),
	.endp0wrstall (endp0wrstall),
	.endp0rd (endp0rd),
	.endp0rddata (endp0rddata),
	.endp0rdready (endp0rdready),
	.endp0rdstall (endp0rdstall),

	// connections to endpoint1 - read only
	.endp1wr (endp1wr),
	.endp1wrready (endp1wrready),
//	.endp1wrstall (endp1wrstall),

	// connections to endpoint3 - read only
	.endp3rd (endp3rd),
	.endp3rddata (endp3rddata),
	.endp3rdready (endp3rdready),
//	.endp3rdstall (endp3rdstall),
	
	// connections to endpoint2 - read only
	.endp2rd (endp2rd),
	.endp2rddata (endp2rddata),
	.endp2rdready (endp2rdready)
//	.endp2rdstall (endp2rdstall)
	);