counter.tan.qmsg

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· QMSG 代码 · 共 14 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 01 16:43:30 2008 " "Info: Processing started: Tue Jan 01 16:43:30 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off counter -c counter " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off counter -c counter" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "EN " "Info: Assuming node EN is an undefined clock" {  } { { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 7 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "EN" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "PULSE " "Info: Assuming node PULSE is an undefined clock" {  } { { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 8 -1 0 } } { "d:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "PULSE" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "EN " "Info: No valid register-to-register paths exist for clock EN" {  } {  } 0}