counter.tan.qmsg

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· QMSG 代码 · 共 14 行 · 第 1/2 页

QMSG
14 行
字号
12
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "PULSE register cntbuf\[0\] register C~reg0 76.92 MHz 13.0 ns Internal " "Info: Clock PULSE has Internal fmax of 76.92 MHz between source register cntbuf\[0\] and destination register C~reg0 (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cntbuf\[0\] 1 REG LC1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'cntbuf\[0\]'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { cntbuf[0] } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns C~reg0 2 REG LC8 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "8.000 ns" { cntbuf[0] C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "8.000 ns" { cntbuf[0] C~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PULSE destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock PULSE to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns PULSE 1 CLK PIN_83 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { PULSE } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns C~reg0 2 REG LC8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "0.000 ns" { PULSE C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE C~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PULSE source 3.000 ns - Longest register " "Info: - Longest clock path from clock PULSE to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns PULSE 1 CLK PIN_83 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { PULSE } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cntbuf\[0\] 2 REG LC1 7 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'cntbuf\[0\]'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "0.000 ns" { PULSE cntbuf[0] } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE cntbuf[0] } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE cntbuf[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "8.000 ns" { cntbuf[0] C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE cntbuf[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "C~reg0 EN PULSE 11.000 ns register " "Info: tsu for register C~reg0 (data pin = EN, clock pin = PULSE) is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns EN 1 CLK PIN_81 9 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'EN'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { EN } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns C~reg0 2 REG LC8 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "8.000 ns" { EN C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "10.000 ns" { EN C~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PULSE destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock PULSE to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns PULSE 1 CLK PIN_83 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { PULSE } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns C~reg0 2 REG LC8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "0.000 ns" { PULSE C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE C~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "10.000 ns" { EN C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE C~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "EN COUNT\[3\] COUNT\[3\]~reg0 15.000 ns register " "Info: tco from clock EN to destination pin COUNT\[3\] through register COUNT\[3\]~reg0 is 15.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN source 10.000 ns + Longest register " "Info: + Longest clock path from clock EN to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns EN 1 CLK PIN_81 9 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'EN'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { EN } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns COUNT\[3\]~reg0 2 REG LC6 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC6; Fanout = 1; REG Node = 'COUNT\[3\]~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "8.000 ns" { EN COUNT[3]~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "10.000 ns" { EN COUNT[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNT\[3\]~reg0 1 REG LC6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 1; REG Node = 'COUNT\[3\]~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { COUNT[3]~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns COUNT\[3\] 2 PIN PIN_10 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'COUNT\[3\]'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "4.000 ns" { COUNT[3]~reg0 COUNT[3] } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "4.000 ns" { COUNT[3]~reg0 COUNT[3] } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "10.000 ns" { EN COUNT[3]~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "4.000 ns" { COUNT[3]~reg0 COUNT[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "C~reg0 EN PULSE -3.000 ns register " "Info: th for register C~reg0 (data pin = EN, clock pin = PULSE) is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PULSE destination 3.000 ns + Longest register " "Info: + Longest clock path from clock PULSE to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns PULSE 1 CLK PIN_83 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { PULSE } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns C~reg0 2 REG LC8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "0.000 ns" { PULSE C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE C~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns EN 1 CLK PIN_81 9 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 9; CLK Node = 'EN'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { EN } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns C~reg0 2 REG LC8 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "8.000 ns" { EN C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "10.000 ns" { EN C~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "10.000 ns" { EN C~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "PULSE C C~reg0 8.000 ns register " "Info: Minimum tco from clock PULSE to destination pin C through register C~reg0 is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PULSE source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock PULSE to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns PULSE 1 CLK PIN_83 5 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 5; CLK Node = 'PULSE'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { PULSE } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns C~reg0 2 REG LC8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "0.000 ns" { PULSE C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE C~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns C~reg0 1 REG LC8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'C~reg0'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "" { C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns C 2 PIN PIN_9 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'C'" {  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "4.000 ns" { C~reg0 C } "NODE_NAME" } } } { "D:/051750/freqm/counter/counter.vhd" "" "" { Text "D:/051750/freqm/counter/counter.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "4.000 ns" { C~reg0 C } "NODE_NAME" } } }  } 0}  } { { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "3.000 ns" { PULSE C~reg0 } "NODE_NAME" } } } { "D:/051750/freqm/counter/db/counter_cmp.qrpt" "" "" { Report "D:/051750/freqm/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "D:/051750/freqm/counter/db/counter.quartus_db" { Floorplan "" "" "4.000 ns" { C~reg0 C } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 01 16:43:30 2008 " "Info: Processing ended: Tue Jan 01 16:43:30 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}
12

counter.tan.qmsg - 源码说明

本页面展示了「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」中的 counter.tan.qmsg 源码文件，采用 QMSG 编程语言编写，共 14 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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