selector.tan.qmsg

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· QMSG 代码 · 共 13 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 03 15:18:43 2007 " "Info: Processing started: Mon Dec 03 15:18:43 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off selector -c selector " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off selector -c selector" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SIG " "Info: Assuming node SIG is an undefined clock" {  } { { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 8 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SIG" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SIG register SIG2 register SIG2 76.92 MHz 13.0 ns Internal " "Info: Clock SIG has Internal fmax of 76.92 MHz between source register SIG2 and destination register SIG2 (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIG2 1 REG LC1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "" { SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.000 ns SIG2 2 REG LC1 2 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "8.000 ns" { SIG2 SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 100.00 % " "Info: Total cell delay = 8.000 ns ( 100.00 % )" {  } {  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "8.000 ns" { SIG2 SIG2 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SIG destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock SIG to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns SIG 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "" { SIG } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns SIG2 2 REG LC1 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "0.000 ns" { SIG SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SIG source 3.000 ns - Longest register " "Info: - Longest clock path from clock SIG to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns SIG 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "" { SIG } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns SIG2 2 REG LC1 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "0.000 ns" { SIG SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } }  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "8.000 ns" { SIG2 SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } }  } 0}