selector.tan.qmsg

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· QMSG 代码 · 共 13 行 · 第 1/2 页

{ "Info" "ITDB_FULL_TCO_RESULT" "SIG En SIG2 17.000 ns register " "Info: tco from clock SIG to destination pin En through register SIG2 is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SIG source 3.000 ns + Longest register " "Info: + Longest clock path from clock SIG to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns SIG 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "" { SIG } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns SIG2 2 REG LC1 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "0.000 ns" { SIG SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIG2 1 REG LC1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "" { SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns En~100 2 COMB LC5 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC5; Fanout = 1; COMB Node = 'En~100'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "9.000 ns" { SIG2 En~100 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns En 3 PIN PIN_11 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'En'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "4.000 ns" { En~100 En } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "13.000 ns" { SIG2 En~100 En } "NODE_NAME" } } }  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "13.000 ns" { SIG2 En~100 En } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[0\] En 15.000 ns Longest " "Info: Longest tpd from source pin SW\[0\] to destination pin En is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns SW\[0\] 1 PIN PIN_52 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 5; PIN Node = 'SW\[0\]'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "" { SW[0] } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns En~100 2 COMB LC5 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC5; Fanout = 1; COMB Node = 'En~100'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "9.000 ns" { SW[0] En~100 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns En 3 PIN PIN_11 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'En'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "4.000 ns" { En~100 En } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 86.67 % " "Info: Total cell delay = 13.000 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.33 % " "Info: Total interconnect delay = 2.000 ns ( 13.33 % )" {  } {  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "15.000 ns" { SW[0] En~100 En } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "SIG En SIG2 17.000 ns register " "Info: Minimum tco from clock SIG to destination pin En through register SIG2 is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SIG source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock SIG to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns SIG 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "" { SIG } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns SIG2 2 REG LC1 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "0.000 ns" { SIG SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIG2 1 REG LC1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 2; REG Node = 'SIG2'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "" { SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns En~100 2 COMB LC5 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC5; Fanout = 1; COMB Node = 'En~100'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "9.000 ns" { SIG2 En~100 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns En 3 PIN PIN_11 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'En'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "4.000 ns" { En~100 En } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "13.000 ns" { SIG2 En~100 En } "NODE_NAME" } } }  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "3.000 ns" { SIG SIG2 } "NODE_NAME" } } } { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "13.000 ns" { SIG2 En~100 En } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SIG Pulse 15.000 ns Shortest " "Info: Shortest tpd from source pin SIG to destination pin Pulse is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns SIG 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'SIG'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "" { SIG } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns Pulse~9 2 COMB LC3 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC3; Fanout = 1; COMB Node = 'Pulse~9'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "8.000 ns" { SIG Pulse~9 } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns Pulse 3 PIN PIN_12 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'Pulse'" {  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "4.000 ns" { Pulse~9 Pulse } "NODE_NAME" } } } { "d:/051750/freqm/selector/selector.vhd" "" "" { Text "d:/051750/freqm/selector/selector.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 93.33 % " "Info: Total cell delay = 14.000 ns ( 93.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.67 % " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" {  } {  } 0}  } { { "d:/051750/freqm/selector/db/selector_cmp.qrpt" "" "" { Report "d:/051750/freqm/selector/db/selector_cmp.qrpt" Compiler "selector" "UNKNOWN" "V1" "d:/051750/freqm/selector/db/selector.quartus_db" { Floorplan "" "" "15.000 ns" { SIG Pulse~9 Pulse } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 03 15:18:44 2007 " "Info: Processing ended: Mon Dec 03 15:18:44 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}