lcd_decoder.vhd

采用VHDL语言编写的万年历程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd_decoder is
    Port ( in1 : in std_logic_vector(3 downto 0);
           out1 : out std_logic_vector(7 downto 0);
           clk : in std_logic);
end lcd_decoder;

architecture Behavioral of lcd_decoder is

begin
    process(in1,clk)
	 begin
	    if rising_edge(clk)then
		    case in1 is
			      when "0000"=>out1<="00110000";--0
					when "0001"=>out1<="00110001";--1
					when "0010"=>out1<="00110010";--2
					when "0011"=>out1<="00110011";--3
					when "0100"=>out1<="00110100";--4
					when "0101"=>out1<="00110101";--5
					when "0110"=>out1<="00110110";--6
					when "0111"=>out1<="00110111";--7
					when "1000"=>out1<="00111000";--8
					when "1001"=>out1<="00111001";--9
					when "1010"=>out1<="01000001";--A
					when "1011"=>out1<="01000010";--B
					when "1100"=>out1<="01000011";--C
					when "1101"=>out1<="01000100";--D
					when "1110"=>out1<="01000101";--E
					when "1111"=>out1<="01000110";--F
					when others=>out1<="00111111";--?
			 end case;
		  end if;
	   end process;



end Behavioral;