decoder_duanxuan.vhd

来自「多功能秒表的设计」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder_duanxuan IS
  PORT (count_in: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
        y: OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END decoder_duanxuan;
ARCHITECTURE behave OF decoder_duanxuan IS
SIGNAL indata:  STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN 
   indata<=count_in;
PROCESS(indata)
   BEGIN
       CASE indata IS
           WHEN "000"=>y<="000001";
           WHEN "001"=>y<="000010";
           WHEN "010"=>y<="000100";
           WHEN "011"=>y<="001000";
           WHEN "100"=>y<="010000";
           WHEN "101"=>y<="100000";
		   WHEN OTHERS=>y<="000000";
       END CASE;
   END PROCESS;
END behave;