disp_count.vhd

来自「多功能秒表的设计」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--**************************************
ENTITY disp_count IS
  PORT(disp_clk: IN STD_LOGIC;
       qout: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END disp_count;
--**************************************
ARCHITECTURE behave OF disp_count IS
    SIGNAL coun_6:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
  PROCESS(disp_clk)
   BEGIN
     IF(disp_clk'EVENT AND disp_clk='1')THEN 
        IF (coun_6=5) THEN 
              coun_6<="000";
        ELSIF(coun_6<5) THEN
			coun_6<=coun_6+1;
		END IF;
     END IF;
  END PROCESS;
 qout<=coun_6;
END behave;