mux_24_4.vhd

来自「多功能秒表的设计」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*****************************************
ENTITY mux_24_4 IS
  PORT
   ( min_shi: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 min_ge: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 sec_shi: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 sec_ge: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 hao_shi: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  	 hao_ge: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	 count:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
	 bcd:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0)	
	);
END mux_24_4;
--*****************************************
ARCHITECTURE behave OF mux_24_4 IS
   BEGIN
	bcd<=hao_ge WHEN count=0 ELSE
			hao_shi WHEN count=1 ELSE
			sec_ge WHEN count=2 ELSE
			sec_shi WHEN count=3 ELSE
			min_ge WHEN count=4 ELSE
			min_shi WHEN count=5 ELSE
 		    "1111";
END behave;